Serial Ports | Intel 820E instruction

D

C

B

A

8

7

Serial Ports

VCC3_3SBY
R17	10K
					CR2
			RI_CR	3	BAT54C
9 ICH_RI#			RI_CR	3	1
9 ICH_RI#
					2
3	Q1	R70	47K
2N7002LT1	3
2N7002LT1	1	1	RI_Q
	2
2		R69	47K
		R69	47K	C92
				1UF

8

7

6

5

VCC5

VCC12

U4

	20	GD75232		1
	20	VCC	VCC12	1
DCD#0	19	VCC	VCC12	2
DCD#0	19	RY0	RA0	2
12	18	RY0	RA0	3
RXD0	18	RY1	RA1	3
12	17	RY1	RA1	4
DSR#0	17	RY2	RA2	4
12	16	RY2	RA2	5
DTR#0	16	DA0	DY0	5
12	15	DA0	DY0	6
TXD0	15	DA1	DY1	6
12	14	DA1	DY1	7
CTS#0	14	RY3	RA3	7
12	13	RY3	RA3	8
RTS#0	13	DA2	DY2	8
12	12	DA2	DY2	9
RI#0	12	RY4	RA4	9
12	11	RY4	RA4	10		VCC12-
	11	GND	VCC-12	10		VCC12-

VCC5

VCC12

U6

	20	GD75232		1
	20	VCC	VCC12	1
DCD#1	19	VCC	VCC12	2
DCD#1	19	RY0	RA0	2
12	18	RY0	RA0	3
RXD1	18	RY1	RA1	3
12	17	RY1	RA1	4
DSR#1	17	RY2	RA2	4
12	16	RY2	RA2	5
DTR#1	16	DA0	DY0	5
12	15	DA0	DY0	6
TXD1	15	DA1	DY1	6
12	14	DA1	DY1	7
CTS#1	14	RY3	RA3	7
12	13	RY3	RA3	8
RTS#1	13	DA2	DY2	8
12	12	DA2	DY2	9
RI#1	12	RY4	RA4	9
12	11	RY4	RA4	10			VCC12-
	11	GND	VCC-12	10			VCC12-
		GND	VCC-12

6

5

4

3

2

1

											COM1
											J6
											DB25_DB9_STK
DCD0_C										A1	DCD
DSR0_C										A6	DSR
RXD0_C										A2	RXD
RTS0_C										A7	RTS
TXD0_C										A3	TXD
CTS0_C										A8	CTS
DTR0_C										A4	DTR
RI0_C										A9	RI
										A5	GND
4	CP1		2	CP1	4	CP8	2	CP8
5	100PF 3	CP1	7	100PF 1	CP1 5	100PF 3	CP8 7	100PF 1		CP8
	100PF 3	CP1		100PF 1	CP1 5	100PF 3	CP8 7	100PF 1		CP8
	6	100PF		8	100PF	6	100PF	8		100PF

									COM2
									J7
DCD1_C								1	2
RXD1_C								3	4
DSR1_C								5	6
DTR1_C								7	8
TXD1_C								9	10
CTS1_C
RTS1_C
RI1_C
4	CP7	3	CP7	5	100PF	7	100PF		COM2 is a 2x5 pin header for a cabled port.
5	100PF 2	CP7 6	100PF 6	100PF 4	CP6 1	CP7 2	CP6 8	100PF
	7	100PF	3	CP6	8	100PF	1	CP6

		TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD					REV:
		SERIAL PORTS				DRAWN BY:	0.5
				R	PCG PLATFORM DESIGN	DRAWN BY:	PROJECT:
				R	PCG PLATFORM DESIGN	PCG AE	Camino2
					1900 PRAIRIE CITY ROAD	PCG AE	Camino2
					FOLSOM, CALIFORNIA 95630	LAST REVISED:	SHEET:
					FOLSOM, CALIFORNIA 95630	3-20-2000_10:15	30 OF 40
						3-20-2000_10:15	30 OF 40
4	3				2	1

D

C

B

A

Image 226

Intel 820E manual Serial Ports

Contents

Intel 820E Chipset Design Guide Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Tables Mil Stack-Up 135 Revision History Rev Description Date Introduction About This Design Guide Reference Documents System Overview Memory Controller Hub MCH Chipset ComponentsController Hub 2 ICH2 ISA Bridge FWH Flash BiosBandwidth Summary Intel 820E Chipset Platform Bandwidth Summary System Configuration MCH UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Streaming Simd Extensions Platform InitiativesDirect Rambus RAM Rdram AGP Expanded USB Support Integrated LAN ControllerUltra ATA/100 Support Manageability SMBus Function DisableIntruder Detect Interrupt Controller 9. AC’97 C AC’97 Connections Ebga Low-Pin-Count LPC Interface This page is intentionally left blank General Recommendations Component Quadrant Layout MCH Intel 820E Chipset Component Placement Sample ATX and NLX MCH/ICH2 Component Placement Core Chipset Routing Recommendations Primary-Side MCH Core Routing Example ATX Secondary-Side MCH Core Routing Example ATX Source-Synchronous Strobing Data Strobing Example AGP 2× Data/Strobe Association Differential Clocking/StrobingDirect RDRAM* Interface Data Associated Strobe Stack-Up Direct RDRAM* Layout Guidelines RSL Routing Placement Guidelines for Motherboard Routing LengthsReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example RSL Termination Direct Rdram Termination Direct RDRAM* Ground Plane Reference Direct RDRAM* Termination Example Plane GND Plane Direct RDRAM* Connector Compensation Equation 1. Approximate Copper Tab Area Calculation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer RSL and Clocking Signal Routing Layer Capacitance pF Section B See Note, Bottom Layer Flood Signal RSL Signal Layer Alternation Length Matching Methods RSL Routing Layer Requirements Equation 2. Rdram RSL Signal Trace Length Calculation Equation 3. Rdram Clock Signal Trace Length Calculation Via Compensation Length Matching and Via Compensation Example Signal Ball on Nominal Package Direct RDRAM* Reference Voltage High-Speed Cmos Routing SIO Routing High-Speed Cmos Termination Suspend-to-RAM Shunt Transistor Rdram Cmos Shunt Transistor RSL Signals High-Speed Serial Clocks Direct RDRAM* Design ChecklistSignal List Direct RDRAM* Clock Routing Intel 820E Chipset If Signal Routed from MCH Primary side AGP Interface Signal Groups AGP Signal Groups Interfaces 6 Inches 2 × Timing Domain Routing Guidelines3 ×/4× Timing Domain Routing Guidelines AGP 2.0 Data/Strobe Associations Interfaces 6 Inches and 7.25 Inches AGP 2×/4× Routing Example for Interfaces 6 Inches All AGP Interfaces Signal Maximum Trace Spacing Length Relative ToAGP 2.0 Routing Summary AGP 2.0 Routing Summary1,2 Recommendations AGP Clock RoutingGeneral AGP Routing Guidelines Decoupling Vddq Generation and TYPEDET# Ground Reference TYPDET#/VDDQ Relationship TYPEDET# on Add-in Card DDQ Supplied by MB Vref Generation for AGP 2.0 2× and 4× AGP Vddq Generation Example Circuit AGP 2.0 Vref Generation and Distribution AGP Pull-Ups Compensation16 k Ω Connector Universal Connector AGP Signal Voltage Tolerance ListConnector / Add-in Card Interoperability Motherboard / Add-in Card Interoperability AGP Universal Retention Mechanism RM AGP Left-Handed Retention Mechanism AGP Left-Handed RM Keep-Out Information AMP P/N Hub Interface Signal Routing Example Hub Interface Bit Hub Interface Buffer Configuration Setting Bit Hub Interface Data SignalsBit Hub Interface Strobe Signals Bit Hub Interface Routing Guidelines Bit Hub Interface Hubref Generation Circuit Specifications MCH ICH2 Hlrefa Hubref Bit Hub Interface Rcomp Resistor Values Bit Hub Interface CompensationBit Hub Interface Decoupling Guidelines Component Hub Interface Trace Rcomp Resistor Value System Bus Ground Plane Reference Additional Host Bus GuidelinesMinimizing Crosstalk on the AGTL+ Interface Additional Considerations IDE InterfaceCable Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side Cable Detection Combination Host-Side/Device-Side IDE Cable Detection Device-Side Cable Detection Device-Side IDE Cable Detection Primary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# Sddreq Secondary IDE Connector RequirementsSiordy IRQ15 SDDACK# 13. AC’97 ICH2 AC’97- Codec Connection Intel 820E Chipset Motherboard CNR Board CNR AC97RESET# Signal DescriptionsCDCDNENAB# Valid Codec Configurations Valid Codec ConfigurationsCodec Configurations Invalid Codec Configurations 13.3. AC’97 Routing USB Using Native USB InterfaceMotherboard Implementation ISA Support Recommended USB trace characteristicsDisabling the Native USB Interface of ICH2 16. I/O Apic Design Recommendation SMBus/SMLink Interface Pull-Up Requirements for SMBus and SMLink Signals SMBus / SMLink Use Implementation PCI RTC RTC Crystal External Capacitors RTC External Battery Connection RTC Layout Considerations RTC External Rtcrst Circuit Rtcrst External Circuit for ICH2 RTC Vbias DC Voltage and Noise Measurements Spkr Pin ConsiderationRTC Routing Guidelines RTC-Well Input Strap Requirements ICH2 Pirq Routing Function in ICH2 using the PCI IRQ in IoapicUsage of I/O Apic Interrupt Inputs 16 through PIRQA# PIRQB# PIRQC# PIRQD# LAN Connect Component Connection FeaturesLAN Layout Guidelines PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd LAN Design Guide Section Reference ICH2 LAN Interconnect GuidelinesLayout Section Previous Design Guide Section Point-to-Point Interconnect Bus TopologiesLOM/CNR Interconnect Configuration Signal Routing and LayoutLength Requirements for Figure Impedances Crosstalk ConsiderationLine Termination General LAN Routing Guidelines and Considerations General Trace Routing Considerations Power and Ground Connections Trace Geometry and Length Ground Plane Separation Layer Board Design Design Guide 111 Crystals and Oscillators Guidelines for Intel 82562EH Component PlacementIntel 82562EH Home/PNA* Guidelines Related Documents Phoneline Hpna Termination Intel 82562EH Component Termination Eeprom Critical DimensionsLPF Distance Priority Guideline Intel 82562ET / Intel 82562EM Component Guidelines Distance from LPF to Phone RJ11 Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Reducing Circuit Inductance Terminating Unused Connections Intel 82562ET/EM Disable Guidelines LAN Disable Circuit Lancl Dual-Footprint Analog Interface ICH2 Decoupling Recommendations Power Plane/Pins # Decoupling Capacitor ValueDecoupling Capacitor Recommendation Decoupling Capacitor Layout In-Circuit FWH Flash Bios Programming FWH Flash Bios GuidelinesFWH Flash Bios VPP Design Guidelines Checklist Items Recommendations Reason/Effect ICH2 Design ChecklistPCI Interface LAN Interface FWH Flash Bios InterfaceHub Interface Eeprom Interface PIRQ#H Interrupt InterfacePIRQ#DA PIRQ#E USB Interface GpioVCCSUS3.3 Processor Signals RTC System ManagementAC’97 Spkr Miscellaneous SignalsPower 5VREF SUS IDE Checklist Checklist Items ISA Bridge ChecklistICH2 AD22 / ISA IDE Interface ICH2 Layout ChecklistBit Hub Interface USB LAN Connect I/F ICH2 Decoupling CK-SKS Clocking Layout Recommendations Yes 138 Design Guide Terminology and Definitions Term Definition 140 Design Guide AGTL+ Design Guidelines Guideline Methodology Equation 5. Hold Time Equation 4. Setup TimeInitial Timing Analysis Equation 6. Maximum Flight Time AGTL+ Parameters for Example Calculations1,2 IC Parameters Pentium Intel Example Tfltmax Calculations for 133 MHz Bus1 Driver Receiver Clk Methodology Determine the Desired General Topology, Layout, and RoutingPre-Layout Simulation Sensitivity Analysis Monte Carlo Analysis Simulation Criteria Place and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsLayout and Route Board Trace Width Space Guidelines Host Clock Routing Apic Data Bus RoutingCrosstalk Type Trace WidthSpace Ratio Intersymbol Interference Post-Layout Simulation Crosstalk Analysis ValidationMeasurements Flight Time Simulation Flight Time Hardware Validation Equation 8. Valid Delay EquationSET Q CLR Q AGTL+ TheoryTiming Requirements Crosstalk Theory Aggressor and Victim Networks Potential Termination Crosstalk Problems More Details and Insight Textbook Timing Equations Power Distribution Effective Impedance and Tolerance/Variation One Signal Layer and One Reference Plane Reference Planes and PCB Stack-Up Layer Switch with Multiple Reference Planes Same Type High-Frequency Decoupling One Layer with Multiple Reference Planes Clock Routing Ringback Levels Vref Guard BandOverdrive Region Conclusion Flight Time Definition and Measurement Intel 820E Chipset Platform System Clocks Clock GenerationNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Platform Clock SkewsLPCCLK, Pciclk Intel 820E Chipset Clock Routing Guidelines1,2 ±TBD3 Intel 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component 1 .318 MHz Crystal to CK133 Component Placement and Interconnection Layout Requirements2. CK133 to Drcg MCH-to-DRCG Routing Diagram MCH to Drcg Trace Geometry DRCG-to-RDRAM ChannelTrace Length Clock From Length inches Section Differential Clock Routing Diagram Sections A, C & D Component Nominal Value Drcg Impedance Matching CircuitExternal Drcg Component Values1,2 CMID, CMID2 Series Termination Resistors for CK133 Clock Outputs AGP Clock Routing GuidelinesClock Routing Guidelines for Intel PGA370 Designs Drcg Layout Example Unused Output Termination Unused OutputsDecoupling Recommendation for CK133 and Drcg Buffer Name CC Range Impedance If Unused Output Drcg Frequency Selection Table and Jitter Specification Drcg Frequency Selection and the DRCG+ DRCG+ Frequency Selection Schematic DRCG+ Frequency Selection Stack-Up Requirement PCB Materials Design Process Test Coupon Design Guidelines Stack-Up Examples Recommended Stack-UpInner-Layer Routing Sample SM max Resin % Impedance Calculation Tools Field Solver vs. Zcalc Testing Board Impedance Board Impedance/Stack-up Summary 182 Design Guide Terminology and Definitions Power DeliveryTerm Definition Intel 820E Chipset Power Delivery Example Dual Switch VCC Vbsy V and 2.5 V Power Sequencing Schottky Diode 3VSB ICH2 1.8 V / 3.3 V Power Sequencing VSB Example 1.8V/3.3V Power Sequencing Circuit 4 .3V/V5REF Sequencing Option 1 Reduce the Clock Frequency During Initialization Excessive Power Consumption by 64/72-Mbit RdramVref Use a GPO to Reduce Drcg Frequency ICH2 Power Plane Split Example of ICH2 Power Plane Split Intel 820E Chipset Component Thermal Design Power Thermal Design PowerFeatures Component Thermal Design Power 133/400 MHz Glue Chip Vendors Vendor Intel Contact Contact Information Appendix a Reference Design Schematics Uniprocessor Reference Design Feature Set 196 Design Guide Prairie City Road REVDrawn by PCG Platform Design Project PCG AE FOLSOM, California Last Revised Sheet Block Diagram Device Table AN9 AK8AH8 AL9 Gtlref CPURST#R2 DBRESET#VCMOS15 Tckr TDI Tmsr Clock Synthesizer Connagpref Hubref RamrefrRamref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host GAD1 GAD2 GAD0GAD0 GAD1 GAD2 GAD3 AD2 AD0AD1 AD3 Vbatcr 1UF ACRESET#CR4 Rtcrstjp NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 NC1 GndaFwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 TERMDQA80 SWP RSRV4/RESETRSRV4/RESET SWP Rimm LDQA0 Super I/O AC’97 Audio Micinc Micinr MicinfbMicin DB15AUDSTK Communication And Network Riser CNR RP7 Stubs on AC97 LinkACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 ACSDATAIN0CNR Acsynccnr Acsdataoutcnr LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH H1138ARAGONITE LAN RJ45 For 82562ET/EMLanactled R381LANCLKX2 25MHZY5 Xtal Y2 Xtal LANCLKX1 LAN Option Intel PART# Stuff for 82562EH SW1 Power SWPower LED VCC12 Irtx USBAGP+ B4 Usbagp AGP4XU20 AGPOC#TYPEDET# Agpclkconn B7 CLK Ptms VCC5 VCC12PCI3CON PTRST# Ptck Ptdi PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy Game Port VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Vccvid REV Project VRM Fault VRM IFBFAULT# IFB Imax VRM G1 VRM G2 Voltage Regulators VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH 1UF-X7RVCC33SBYTG VCC33SBYSW VCC25SBY SBY ITH R Power Connector BPRI# DBSY# HREQ#0 PCI/AGP Pullups/Pulldowns Rambus* Termination Termcmd Termsck Decoupling VCMOS18SBY Bulk Decoupling Drawn by PCG Platform Design Project PCG AE Revision History Revision History Drawn by PCG Platform Design Project PCG AE TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# Hub Interface Connector For debug onlyProbe Connector HL8 HL4 HL5 HL6 HL7