Design Guide
Intel 820E Chipset
Intel 820E Chipset
Contents
1.1
102
AGTL+
191
Figures
CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade
Mil Stack-Up
Tables
135
Rev Description Date
Revision History
About This Design Guide
Introduction
Reference Documents
System Overview
Controller Hub 2 ICH2
Chipset Components
Memory Controller Hub MCH
Intel 820E Chipset Platform Bandwidth Summary
FWH Flash Bios
Bandwidth Summary
ISA Bridge
MCH
System Configuration
UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs
AGP
Platform Initiatives
Direct Rambus RAM Rdram
Streaming Simd Extensions
Manageability
Integrated LAN Controller
Ultra ATA/100 Support
Expanded USB Support
Interrupt Controller
Function Disable
Intruder Detect
SMBus
9. AC’97
Ebga
C AC’97 Connections
Low-Pin-Count LPC Interface
This page is intentionally left blank
Component Quadrant Layout
General Recommendations
MCH
Sample ATX and NLX MCH/ICH2 Component Placement
Intel 820E Chipset Component Placement
Primary-Side MCH Core Routing Example ATX
Core Chipset Routing Recommendations
Secondary-Side MCH Core Routing Example ATX
Data Strobing Example
Source-Synchronous Strobing
Data Associated Strobe
Differential Clocking/Strobing
Direct RDRAM* Interface
AGP 2× Data/Strobe Association
Direct RDRAM* Layout Guidelines
Stack-Up
Reference Trace Description Maximum Trace Length
Placement Guidelines for Motherboard Routing Lengths
RSL Routing
RSL Routing Diagram
Secondary-Side RSL Breakout Example
Direct Rdram Termination
RSL Termination
Direct RDRAM* Termination Example
Direct RDRAM* Ground Plane Reference
GND Plane
Plane
Equation 1. Approximate Copper Tab Area Calculation
Direct RDRAM* Connector Compensation
Copper Tab Area Calculation
Connector Compensation Example
Section a See Note, Top Layer
Section a See Note, Bottom Layer
Section B See Note, Top Layer
Section B See Note, Bottom Layer
RSL and Clocking Signal Routing Layer Capacitance pF
Flood Signal
RSL Signal Layer Alternation
RSL Routing Layer Requirements
Length Matching Methods
Equation 3. Rdram Clock Signal Trace Length Calculation
Equation 2. Rdram RSL Signal Trace Length Calculation
Length Matching and Via Compensation Example
Via Compensation
Signal Ball on Nominal Package
High-Speed Cmos Routing
Direct RDRAM* Reference Voltage
High-Speed Cmos Termination
SIO Routing
Rdram Cmos Shunt Transistor
Suspend-to-RAM Shunt Transistor
Direct RDRAM* Clock Routing
Direct RDRAM* Design Checklist
Signal List
RSL Signals High-Speed Serial Clocks
Intel 820E Chipset
Primary side
If Signal Routed from MCH
AGP
AGP Interface Signal Groups
Signal Groups
AGP 2.0 Data/Strobe Associations
2 × Timing Domain Routing Guidelines
3 ×/4× Timing Domain Routing Guidelines
Interfaces 6 Inches
AGP 2×/4× Routing Example for Interfaces 6 Inches
Interfaces 6 Inches and 7.25 Inches
AGP 2.0 Routing Summary1,2
Signal Maximum Trace Spacing Length Relative To
AGP 2.0 Routing Summary
All AGP Interfaces
Decoupling
AGP Clock Routing
General AGP Routing Guidelines
Recommendations
Ground Reference
Vddq Generation and TYPEDET#
TYPEDET# on Add-in Card DDQ Supplied by MB
TYPDET#/VDDQ Relationship
AGP Vddq Generation Example Circuit
Vref Generation for AGP 2.0 2× and 4×
AGP 2.0 Vref Generation and Distribution
16 k Ω
Compensation
AGP Pull-Ups
Motherboard / Add-in Card Interoperability
AGP Signal Voltage Tolerance List
Connector / Add-in Card Interoperability
Connector Universal Connector
AGP Left-Handed Retention Mechanism
AGP Universal Retention Mechanism RM
AMP P/N
AGP Left-Handed RM Keep-Out Information
Hub Interface
Hub Interface Signal Routing Example
Bit Hub Interface Routing Guidelines
Bit Hub Interface Data Signals
Bit Hub Interface Strobe Signals
Bit Hub Interface Buffer Configuration Setting
MCH ICH2 Hlrefa Hubref
Bit Hub Interface Hubref Generation Circuit Specifications
Component Hub Interface Trace Rcomp Resistor Value
Bit Hub Interface Compensation
Bit Hub Interface Decoupling Guidelines
Bit Hub Interface Rcomp Resistor Values
Minimizing Crosstalk on the AGTL+ Interface
Additional Host Bus Guidelines
System Bus Ground Plane Reference
Cable
IDE Interface
Additional Considerations
Combination Host-Side/Device-Side Cable Detection
Cable Detection for Ultra ATA/66 and Ultra ATA/100
Combination Host-Side/Device-Side IDE Cable Detection
Device-Side IDE Cable Detection
Device-Side Cable Detection
Primary IDE Connector Requirements
Siordy IRQ15 SDDACK#
Secondary IDE Connector Requirements
SDCS1# SDCS3# SDIOR# SDIOW# Sddreq
ICH2 AC’97- Codec Connection
13. AC’97
Intel 820E Chipset
Motherboard CNR Board
CNR
CDCDNENAB#
Signal Descriptions
AC97RESET#
Invalid Codec Configurations
Valid Codec Configurations
Codec Configurations
Valid Codec Configurations
13.3. AC’97 Routing
Motherboard Implementation
Using Native USB Interface
USB
Disabling the Native USB Interface of ICH2
Recommended USB trace characteristics
ISA Support
SMBus/SMLink Interface
16. I/O Apic Design Recommendation
SMBus / SMLink Use Implementation
Pull-Up Requirements for SMBus and SMLink Signals
RTC
PCI
External Capacitors
RTC Crystal
RTC Layout Considerations
RTC External Battery Connection
Rtcrst External Circuit for ICH2 RTC
RTC External Rtcrst Circuit
RTC-Well Input Strap Requirements
Spkr Pin Consideration
RTC Routing Guidelines
Vbias DC Voltage and Noise Measurements
Usage of I/O Apic Interrupt Inputs 16 through
Function in ICH2 using the PCI IRQ in Ioapic
ICH2 Pirq Routing
PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd
LAN Connect Component Connection Features
LAN Layout Guidelines
PIRQA# PIRQB# PIRQC# PIRQD#
Layout Section Previous Design Guide Section
ICH2 LAN Interconnect Guidelines
LAN Design Guide Section Reference
LOM/CNR Interconnect
Bus Topologies
Point-to-Point Interconnect
Length Requirements for Figure
Signal Routing and Layout
Configuration
Line Termination
Crosstalk Consideration
Impedances
General Trace Routing Considerations
General LAN Routing Guidelines and Considerations
Trace Geometry and Length
Power and Ground Connections
Ground Plane Separation
Layer Board Design
Design Guide 111
Related Documents
Guidelines for Intel 82562EH Component Placement
Intel 82562EH Home/PNA* Guidelines
Crystals and Oscillators
Intel 82562EH Component Termination
Phoneline Hpna Termination
Distance Priority Guideline
Critical Dimensions
LPF
Eeprom
Distance from LPF to Phone RJ11
Intel 82562ET / Intel 82562EM Component Guidelines
Intel 82562ET/82562EM Component Termination
Distance from Magnetics Module to RJ45
Terminating Unused Connections
Reducing Circuit Inductance
LAN Disable Circuit
Intel 82562ET/EM Disable Guidelines
Lancl
Dual-Footprint Analog Interface
Decoupling Capacitor Recommendation
Power Plane/Pins # Decoupling Capacitor Value
ICH2 Decoupling Recommendations
Decoupling Capacitor Layout
FWH Flash Bios VPP Design Guidelines
FWH Flash Bios Guidelines
In-Circuit FWH Flash Bios Programming
PCI Interface
ICH2 Design Checklist
Checklist Items Recommendations Reason/Effect
Eeprom Interface
FWH Flash Bios Interface
Hub Interface
LAN Interface
PIRQ#E
Interrupt Interface
PIRQ#DA
PIRQ#H
VCCSUS3.3
Gpio
USB Interface
Processor Signals
AC’97
System Management
RTC
5VREF SUS
Miscellaneous Signals
Power
Spkr
IDE Checklist
ICH2 AD22 / ISA
ISA Bridge Checklist
Checklist Items
USB
ICH2 Layout Checklist
Bit Hub Interface
IDE Interface
LAN Connect I/F
ICH2 Decoupling
Layout Recommendations Yes
CK-SKS Clocking
138 Design Guide
Term Definition
Terminology and Definitions
140 Design Guide
Guideline Methodology
AGTL+ Design Guidelines
Equation 6. Maximum Flight Time
Equation 4. Setup Time
Initial Timing Analysis
Equation 5. Hold Time
IC Parameters Pentium Intel
AGTL+ Parameters for Example Calculations1,2
Driver Receiver Clk
Example Tfltmax Calculations for 133 MHz Bus1
Sensitivity Analysis
Determine the Desired General Topology, Layout, and Routing
Pre-Layout Simulation
Methodology
Simulation Criteria
Monte Carlo Analysis
Layout and Route Board
Estimate Component-to-Component Spacing for AGTL+ Signals
Place and Route Board
Crosstalk Type Trace WidthSpace Ratio
Host Clock Routing Apic Data Bus Routing
Trace Width Space Guidelines
Post-Layout Simulation
Intersymbol Interference
Measurements Flight Time Simulation
Validation
Crosstalk Analysis
SET Q CLR Q
Equation 8. Valid Delay Equation
Flight Time Hardware Validation
Timing Requirements
Theory
AGTL+
Aggressor and Victim Networks
Crosstalk Theory
Potential Termination Crosstalk Problems
Textbook Timing Equations
More Details and Insight
Effective Impedance and Tolerance/Variation
Power Distribution
Reference Planes and PCB Stack-Up
One Signal Layer and One Reference Plane
Layer Switch with Multiple Reference Planes Same Type
One Layer with Multiple Reference Planes
High-Frequency Decoupling
Clock Routing
Overdrive Region
Vref Guard Band
Ringback Levels
Flight Time Definition and Measurement
Conclusion
Number Name on CK133 Used for Routed to Frequency Voltage
Clock Generation
Intel 820E Chipset Platform System Clocks
Intel 820E Chipset Platform Clock Distribution
LPCCLK, Pciclk
Intel 820E Chipset Platform Clock Skews
Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max
±TBD3
Intel 820E Chipset Clock Routing Guidelines1,2
CK133/DRCG Pin Name Component
Intel 820E Chipset Platform System Clock Cross-Reference
2. CK133 to Drcg
Component Placement and Interconnection Layout Requirements
1 .318 MHz Crystal to CK133
MCH to Drcg
MCH-to-DRCG Routing Diagram
Clock From Length inches Section
DRCG-to-RDRAM Channel
Trace Length
Trace Geometry
Differential Clock Routing Diagram Sections A, C & D
CMID, CMID2
Drcg Impedance Matching Circuit
External Drcg Component Values1,2
Component Nominal Value
Drcg Layout Example
AGP Clock Routing Guidelines
Clock Routing Guidelines for Intel PGA370 Designs
Series Termination Resistors for CK133 Clock Outputs
Buffer Name CC Range Impedance If Unused Output
Unused Outputs
Decoupling Recommendation for CK133 and Drcg
Unused Output Termination
Drcg Frequency Selection and the DRCG+
Drcg Frequency Selection Table and Jitter Specification
DRCG+ Frequency Selection
DRCG+ Frequency Selection Schematic
PCB Materials
Stack-Up Requirement
Test Coupon Design Guidelines
Design Process
Sample SM max Resin %
Recommended Stack-Up
Inner-Layer Routing
Stack-Up Examples
Field Solver vs. Zcalc
Impedance Calculation Tools
Board Impedance/Stack-up Summary
Testing Board Impedance
182 Design Guide
Term Definition
Power Delivery
Terminology and Definitions
Intel 820E Chipset Power Delivery Example
VCC
Dual Switch
Vbsy
3VSB
V and 2.5 V Power Sequencing Schottky Diode
VSB
ICH2 1.8 V / 3.3 V Power Sequencing
4 .3V/V5REF Sequencing
Example 1.8V/3.3V Power Sequencing Circuit
Vref
Excessive Power Consumption by 64/72-Mbit Rdram
Option 1 Reduce the Clock Frequency During Initialization
Use a GPO to Reduce Drcg Frequency
Example of ICH2 Power Plane Split
ICH2 Power Plane Split
Component Thermal Design Power 133/400 MHz
Thermal Design Power
Features
Intel 820E Chipset Component Thermal Design Power
Vendor Intel Contact Contact Information
Glue Chip Vendors
Reference Design Feature Set
Appendix a Reference Design Schematics Uniprocessor
196 Design Guide
FOLSOM, California Last Revised Sheet
REV
Drawn by PCG Platform Design Project PCG AE
Prairie City Road
Device Table
Block Diagram
AL9
AK8
AH8
AN9
Tckr TDI Tmsr
CPURST#R2 DBRESET#
VCMOS15
Gtlref
Clock Synthesizer
Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host
Hubref Ramrefr
Ramref
Connagpref
GAD2 GAD3
GAD0
GAD0 GAD1
GAD1 GAD2
AD3
AD0
AD1
AD2
Rtcrstjp
ACRESET#
CR4
Vbatcr 1UF
VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29
NC1 Gnda
Fwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36
NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32
Rimm LDQA0
SWP RSRV4/RESET
RSRV4/RESET SWP
TERMDQA80
Super I/O
AC’97 Audio
DB15AUDSTK
Micinr Micinfb
Micin
Micinc
Communication And Network Riser CNR
ACSDATAIN0CNR Acsynccnr Acsdataoutcnr
Stubs on AC97 Link
ACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2
RP7
LAN 82562EH
82562ET/EM
LAN RJ11 For 82562EH
Lanactled
LAN RJ45 For 82562ET/EM
H1138ARAGONITE
LAN Option Intel PART#
25MHZ
Y5 Xtal Y2 Xtal LANCLKX1
R381LANCLKX2
Stuff for 82562EH
VCC12 Irtx
Power SW
Power LED
SW1
Agpclkconn B7 CLK
AGP4XU20 AGPOC#
TYPEDET#
USBAGP+ B4 Usbagp
Ptdi
VCC5 VCC12
PCI3CON PTRST# Ptck
Ptms
PCI Connectors
IDE Connectors
USB Connectors
Port Parallel
Serial Ports
Keyboard/Mouse/Floppy
VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr
Game Port
Imax VRM G1 VRM G2
VRM Fault VRM IFB
FAULT# IFB
Vccvid REV Project
Voltage Regulators
SBY ITH R
1UF-X7R
VCC33SBYTG VCC33SBYSW VCC25SBY
VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH
Power Connector
HREQ#0
BPRI# DBSY#
PCI/AGP Pullups/Pulldowns
Termcmd Termsck
Rambus* Termination
Decoupling
Bulk Decoupling Drawn by PCG Platform Design Project PCG AE
VCMOS18SBY
Revision History Drawn by PCG Platform Design Project PCG AE
Revision History
HL8 HL4 HL5 HL6 HL7
Hub Interface Connector For debug only
Probe Connector
TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB#