Intel 820E manual AGP 2.0 Vref Generation and Distribution

Intel® 820E Chipset

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During a 3.3 V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during a 1.5 V AGP 2.0 operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, such as the example in the following figure.

Figure 39. AGP 2.0 VREF Generation and Distribution

	+12 V
	R7	(Note 2)
1.5-V AGP Card	1 kΩ
		TYPEDET#
	VrefGC
		U6
VDDQ		MOSFET
AGP	REF
deviceGND
	VrefCG

	R9	1%			VDDQ
300 Ω
	R11
200 Ω		1%
				VDDQ
C10			REF GMCH
			GND
0.1 µF

Place C10 close to MCH.

C8

500 pF

R6		R5
1 kΩ		82 Ω
R2		R4
		82 Ω
1 kΩ
		C9
	500 pF

Notes:

1.The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals.

2.R7 is the same resistor as R1 in the figure AGP VDDQ Generation Example Circuit.

3.3-V AGP Card

VDDQ

AGP REF device

GND

+12 V

R7 (Note 2)
1 kΩ	R9
TYPEDET#		VDDQ
	300 Ω 1%

	R11					C8
VrefGC						500 pF
	200 Ω 1%
U6			R6			R5
		VDDQ	1 kΩ			82 Ω
MOSFET	C10	REF GMCH
		GND	R2		R4
	0.1 uF		1 kΩ
					82	Ω
					C9
				500 pF
Place C10 close to MCH.
VrefCG

Notes:

1.The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals.

2.R7 is the same resistor as R1 in the figure AGP VDDQ Generation Example Circuit.

AGP2_Vref_gen-dist

The flexible VREF divider shown in the preceding figure uses an FET switch to switch between the locally generated VREF (for 3.3 V add-in cards) and the source-generated VREF (for 1.5 V add-in cards).

Use of the source-generated VREF at the receiver is optional and is a product implementation issue beyond the scope of this document.

Design Guide 69