Intel 820E manual Lancl

Intel® 820E Chipset

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There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for this design.

Test_En	Isol_Tck	Isol_Ti	Isol_Tex	State
0	0	0	0	Enabled
0	1	1	1	Disabled w/ Clock (low power)
1	1	1	1	Disabled w/out Clock (lowest power)

The four control signals shown in the above table should be configured as follows: Test_En should be pulled-down thru a 100 Ω resistor. The remaining 3 control signals should each be connected thru 100 Ω series resistors to the common node “82652ET/EH_Disable” of the disable circuit.

2.22.6.Intel® 82562ET and Intel® 82562EH Components’ Dual- Footprint Guidelines

These guidelines explain the proper layout for a dual-footprint solution. This configuration allows the developer to install either the Intel 82562EH or Intel 82562ET/82562EM component, with only one motherboard design. The following guidelines are for the Intel 82562ET/82562EH components’ dual- footprint option. The guidelines called out in Sections 2.22.1 and 2.22.4 apply to this configuration. The dual footprint for this particular solution uses a SSOP footprint for the Intel 82562ET component and a TQFP footprint for the Intel 82562EH component. The combined footprint for this configuration is shown in Figure 76 and Figure 77.

Figure 76. Dual-Footprint LAN Connect Interface

	L
			8
	LAN_CL	®	2	S
		Intel	5	S
	LAN_RSTSY	82562EH	6	O
ICH	LAN_RXD[2:	TQF	2
			E	P
	LAN_TXD[2:		T
		Stub
		IO_subsys_dual_footprint_LAN_conn_IF

120 Design Guide