Intel® 820E Chipset
R
Design Guide 93
Figure 56. USB Data Signals
15k
15k
15
15
ICH2
P+
P-
USB Connector
< 1"
< 1"
90
45
45
Driver
Driver
USB Twisted Pair Cable Transmission Line
Motherboard Trace
Motherboard Trace
Optional 47 pF
Optional 47 pF
Recommended USB trace characteristics
Impedance Z0 = 45.4
Line delay = 160.2 ps
Capacitance = 3.5 pF
Inductance = 7.3 nH
Resistance at 20 °C = 53.9 m

2.14.3. Disabling the Native USB Interface of ICH2

The ICH2 native USB interface can be disabled. This can be done when an external PCI based USB
controller is being implemented in the platform. To disable the native USB Interface, ensure the
differential pairs are pulled down thru 15 k resistors, ensure the OC[3:0]# signals are de-asserted by
pulling them up weakly to VCC3SBY, and that both function 2 and 4 are disabled via the
D31:F0;FUNC_DIS register. Ensure that the 48 MHz USB clock is connected to the ICH2 and is kept
running. This clock must be maintained even though the internal USB functio ns are disabled.
2.15. ISA Support
Implementations that require ISA support can benefit from the enhancements of the ICH2, while “ISA-
less” designs are not burdened with the complexity and cost of the ISA subsystem. For an
implementation of an ISA design, contact external suppliers.