Intel® 820E Chipset

R

Interrupts B, D, E, and H service devices internal to the ICH2. Interrupts A, C, F, and G are unused and can be used by PCI slots. The following figure shows an example of IRQ line routing to the PCI slots.

Figure 63. Example PCI IRQ Routing

PIRQA#

PIRQB#

PIRQC#

PIRQD#

ICH2

PIRQE#

PIRQF#

PIRQG#

PIRQH#

INTA

INTB

INTC

INTD

INTA

INTB

INTC

INTD

INTA

INTB

INTC

INTD

INTA

INTB

INTC

INTD

Slot 1

Slot 2

Slot 3

Slot 4

PCI Device 0

PCI Device 5

PCI Device 6

PCI Device C

(AD16 to IDSEL)

(AD21 to IDSEL)

(AD22 to IDSEL)

(AD28 to IDSEL)

 

 

 

PCI_IRQ_routing_ex

The PCI IRQ routing in the previous figure allows the ICH2’s internal functions to have a dedicated IRQ, assuming add-in cards are single-function devices and use INTA. If a P2P bridge card or a multifunction device uses more than one INTn# pin on the ICH2 PCI bus, the ICH2’s internal functions will start sharing IRQs.

Figure 63 is one example. It is up to board designers to route these signals most efficiently for their particular systems. A PCI slot can be routed to share interrupts with any of the ICH2’s internal device/functions.

2.22.LAN Layout Guidelines

The ICH2 provides several options for integrated LAN capability. The platform supports several components, depending on the target market. These guidelines use the Intel 82562ET to refer to both the Intel 82562ET and the Intel 82562EM. The Intel 82562EM is specified in those cases where there is a difference.

LAN Connect Component

Connection

Features

 

 

 

Intel 82562EM

Advanced 10/100 Ethernet

AOL* & Ethernet 10/100 connection

 

 

 

Intel 82562ET

10/100 Ethernet

Ethernet 10/100 connection

 

 

 

Intel 82562EH

1-Mbit HomePNA* LAN

1-Mbit HomePNA connection

 

 

 

Intel developed a dual footprint for the Intel 82562ET and Intel 82562EH components, to minimize the required number of board builds. A single layout with the specified dual footprint allows the OEM to install the LAN connect component appropriate for the market need. Design guidelines are provided for each required interface and connection. Refer to Figure 64 and Table 22 for the corresponding section of the design guide.

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Design Guide

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Intel 820E manual LAN Layout Guidelines, Pirqa# Pirqb# Pirqc# Pirqd#, PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd