Intel 820E manual Clock Synthesizer

8 7 6 5 4 3 2 1

VCC2_5

VCC3_3	Clock Synthesizer
1	L20
	2
	Provide at least one 0.1uF decoupling cap per power pin.
	FBHS01L
	VCC_3_3_CK133_FB

L21	2
1
FBHS01L
VCC2_5_CK133_FB
C180 C190 C192 C199	C171

D

C207 C215 C223 C186 C198 C206 C214 C170

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF

CK133_XIN

Y3

XTAL

U11	4	10	16	23
CK133
	1	2	3	4
	VDD3V	VDD3V	VDD3V	VDD3V

27	39	31	56
VDD3V 5	VDD3V 6	VDD3V 7	VDD25V 1

51	47	43
2	3	4
VDD25V	VDD25V	VDD25V

0.1UF 0.1UF 0.1UF 0.1UF 10UF

D

VCC3_3

VCC3_3

	CK133_XOUT
1	2

14.318MHZ	C189
C185
10PF	10PF

5	XTAL_IN
6
	XTAL_OUT

APIC0

APIC1

APIC2

CPU_DIV2_1 CPU_DIV2_2

53

54

55

50

49

PICCLK_R R155 APICCLK_R APIC2_R CPU_DIV2_1_R

CPU_DIV2_2_R ITPCLK_R R188

22

22R156

22R148

22

APICCLK_CPU APICCLK_ICH

CPU_DIV2

ITPCLK

4

8

Keep stubs on unused outputs as short as possible. Tie CPUCLK and MCHCLK outputs together.

R206 10K R203 10K R202 10K R197 10K R196 10K R192 10K R224 220

2

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

41

42

45

46

CPUHCLK_R

33

CPUCLK3_R

33R189

R184

4

MCHCLK

6

CPUHCLK

4

C

SEL133/100#

4,7

PCISTOP#

CPUSTOP#

CK133_PWRDWN#

SPREAD#

SEL1

SEL0

JP17 JP15 JP14

JP19

JP19 is for debug only.

28SEL133/100#

37PCISTOP#

36CPUSTOP#

35PWRDWN#

34SPREAD#

33SEL1

32SEL0

PCICLK_F

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

PCICLK6

PCICLK7

3V66_0

3V66_1

3V66_2

3V66_3

48MHZ

REF0

REF1

8

9

11

12

14

15

17

18

21

22

25

26

30

2

3

ICHPCLK_R	R165	33
PCLK1_R	R169	R164 33
PCLK2_R		33
PCLK3_R	R186	R183 33
PCLK4_R		33
PCLK5_R		R187 33
FWHPCLK_R R191 33
SIO_PCLK7_R		R194 33
MCH_CLK66_R33		R201

	R195	33
ICH_CLK66_RR210 33
TEST_CLK66_R	R211	33
R221	22
IHC_48MHZ_R
IHC_14MHZ_R	R147	22
R150
SIO_14MHZ_R
22

ICHPCLK

PCLK1

PCLK2

PCLK3

PCLK4

PCLK5

FWHPCLK

SIO_PCLK7

AGPCLK_CONN MCH_CLK66 ICH_CLK66 TEST_CLK66 ICH_48MHZ ICH_14MHZ SIO_14MHZ

8

25

25

26

26

10

12

24

7

9

9

9

12

		C476	C477
	R151	10PF	10PF
		30
R166	30
R170		VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
		CLKTM and CLKTM# RC network must use 5% or better tolerance components.
30				VCC3_3
		VCC2_5
		VCC1_8	2	L22
				1

C

VSS1 VSS2 VSS3 VSS4

VSS5 VSS6 VSS7 VSS8 VSS9

VSS10 VSS11 VSS12

VCC3_3	No stuff R220
	for debug.
	VCC1_8

R220 33

FBHS01L

VCC3_3_DRCG_FB

B

A

H O S T
B U S / R A M B U S			J P 1 3
1 0 0 / 4 0 0			O U T
1 3 3 / 4 0 0		2 - 3
S p r d S p e c t		J P 1 4
E n a b l e d *			IN
D i s a b l e d		O U T
S E L 1 3 3 /1 0 0 #	J P 1 5		J P 1 7	F u n c ti o n
0	IN		IN	A ll o u t p u ts Tri-S ta te
0	IN		O U T	R e s e rve d
0	O U T		IN	A c t ive 1 0 0 M H z , 4 8 M H z P L L in a c tive
0	O U T		O U T	A c t ive 1 0 0 M H z , 4 8 M H z P L L a c t ive
1	IN		IN	Te s t M o d e
1	IN		O U T	R e s e rve d
1	O U T		IN	A c t ive 1 3 3 M H z ,4 8 M H z P L L in a c t ive
1	O U T		O U T	A c t ive 1 3 3 M H z ,4 8 M H z P L L a c tive *

All jumpers may not be required, but are included for test purposes.

1

7

13

19

20

24

52

8

48

44 40 38 29

			8	MULT0_GPIO	R219
VCC3_3
				JP13
				1
				2
				3
				JP13 is for debug only.
R230	10K	R217	10K

DRCG_CTRL

JP26

MULT1_GPIO 1

9

JP202 3

10K R204 10K R199 10K

DRCG_PWRDWN#

STOPB#

MULT0

MULT1

HCLKOUT

7

RCLKOUT

7

U12

C364

C208

C196

C204

C220

C209

DRCG+

1

10

16

22

3

9

0.1UF

0.1UF

0.1UF

0.1UF

10UF

82PF

VDDIR

VDDIPD

VDDO1

VDDO2

VDDP

VDDC

Place C364 next to VDDP

2

REFCLK

12

PWRDN#

39-1%

11

DRCG_CLK

CLKTM

STOPB#

11

15

R182

MULT0

14

CLK

20

51-1%

51-1%

MULT1

18

24

CLKB#

S0

R185

CLKTMRD

R200

C363

7

39-1%

4PF

23

S1

13

GND

6

PCLKM

SYNCLKN

CLKTM#

19

NC

GNDO1

GNDO2

GNDP GNDC

GNDI

DRCG_CLKB#

R205

11

No stuff C363

17

21

4

8

5

C205

0.1UF

TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD

REV:

CLOCK SYNTHESIZER

DRAWN BY:

0.5

R

PCG PLATFORM DESIGN

PROJECT:

PCG AE

Camino2

1900 PRAIRIE CITY ROAD

FOLSOM, CALIFORNIA 95630

LAST REVISED:

SHEET:

3-20-2000_14:02

5 OF 40

B

A

8 7 6 5 4 3 2 1