Intel 820E 6.1.3. ICH2 1.8 V / 3.3 V Power Sequencing

Intel® 820E Chipset
R
188 Design Guide
1.8 VSB
The 1.8 VSB plane powers the logic to the resume well of the ICH2. This should not be used for VCMOS.
The VCMOS described in the 2.5 VSBY section should be powered down in S5. However, the 1.8 VSB
requires power in S5. Refer to the 2.5 VSBY section for information regarding powering the VCMOS (1.8
V) rail.
2.5 V
The 2.5 V plane supplies power to the CK133 and the DRCG system clock generator components.
6.1.3. ICH2 1.8 V / 3.3 V Power Sequencing
The ICH2 has two pairs of associated 1.8 V and 3.3 V supplies. These are (Vcc1_8, Vcc3_3) and
({VccSus1_8, VccSus3_3). The ICH2-m has a third pair (VccLAN1_8, VccLAN3_3). These pairs are
assumed to power up and power down together. The difference between the two associated supplies must
never be greater than 2.0 V. The 1.8 V supply may come up before the 3.3 V supply without violating
this rule. (Although this generally is not practical in a deskto p environment, since the 1.8 V supply is
typically derived from the 3.3 V supply by means of a linear regulator.)
One serious consequence of violating this “2 V Rule” is electrical overstress of oxide layers, resulting in
component damage.
Most ICH2 I/O buffers are driven by the 3.3 V supplies, but are controlled by logic powered by the 1.8 V
supplies. Thus, another consequence of faulty power sequencing arises if the 3.3 V supply comes up first.
In this case the I/O buffers will be in an undefined state until the 1.8 V logic is powered up. Some signals
defined as “input-only” actually have output buffers that a re disabled normally, and the ICH2 may
unexpectedly drive these signals if the 3.3 V supply is active while the 1.8 V supply is not.
Figure 103 is an example power-on sequencing circuit that ensures the 2 V Rule is obeyed. This circuit
uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8 V supply tracks the 3.3 V supply. The NPN
transistor controls the current through PNP from the 3 .3 V supply into the 1.8 V power plane by varying
the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8 V
plane, current will not flow from the 3.3 V supply into 1.8 V plane when the 1.8 V plane reaches 1.8 V.