Intel manual Intel 820E Chipset Platform Clock Distribution

Intel® 820E Chipset

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The MCH uses the same clock for hub interface and AGP. It is important that the hub interface/AGP clocks are routed so as to ensure that the skew requirements are satisfied as follows:

•Between the MCH hub interface/AGP clock and the AGP connector (or device)

•Between the MCH hub interface/AGP clock and the ICH2 hub interface clock

The DRCG reference clock operates at one-half the processor clock frequency. It is an input into the DRCG and is used to generate the Direct RDRAM clock-to-master differential pair (CTM, CTM#).

The DRCG generates one pair of differential Direct RDRAM clocks (CTM, CTM#) from the reference clock generated by the CK133. In addition, the DRCG uses phase information provided by the MCH to phase-align the Direct RDRAM clock with the processor clocks. This phase alignment information is provided to the DRCG via the SYNCLKN and PCLKM pins.

Figure 86. Intel® 820E Chipset Platform Clock Distribution

A	Processor	C	Processor
				RDRAM	RDRAM
	CLK		CLK
B		D
	PICCLK		PICCLK	RCLK TCLK	RCLK TCLK

	CPUCLK
	APIC
	CPUCLK
	APIC
	CPUCLK		MCH		CTM
	3V66
					CFM
		E
			HCLKIN	PHASEINFO			PHASEINFO
CPU_DIV2		F	CLK66				Q REFCLK DRCG
	3V66				P	CLK	AGP
	APIC
	PCICLK*	G	APICCLK		ICH	CONNECTOR
	3V66	H
CK133			PCICLK		N	CLK
	REF	I	CLK66				LPC
	48Hz	J
			CLK14			Flash BIOS
		K	CLK48		M
	PCICLK					CLK	LPC
	PCICLK
	PCICLK	L	CLK
			PCI SLOTS

L CLK

PCI SLOTS

L CLK

PCI SLOTS

L CLK

PCI SLOTS

* The free-running PCI clock should be connected to the ICH.

RDRAM		RDRAM	TERM
RCLK TCLK	RCLK TCLK

clock_dist

164 Design Guide