Intel manual Intel 820E Chipset Platform Clock Skews, LPCCLK, Pciclk

								Intel® 820E Chipset
	R
Table 56. Intel® 820E Chipset Platform Clock Skews
		Clock Symbols (see	Relationship			Skew				Notes
		Figure 86)
				Pin-to-Pin (ps)		Board (ps)		Total (ps)
				Min.	Max.	Min.	Max.	Min.	Max.
		A leads C	PGA370 HCLK to PGA370	-175	+175	-125	+125	-300	+300	1, 7
			HCLK (DP only)
		A leads E	and
		(or C leads E)	PGA370 HCLK to MCH
			HCLK (DP only)
		A leads E	PGA370 HCLK to MCH HCLK	0	0	-125	+125	-125	+125	2, 3, 7
			(UP only)
		P leads F	MCH CLK66 to AGP graphics	0	0	-125	+125	-125	+125	4, 8
			device AGPCLK
		L leads another L	PCICLK to PCICLK	-500	+500	-1500	+1500	-2000	+2000
		(or L leads H)
		I leads H	ICH2 CLK66 leads ICH2	+1500	+4000	-500	+500	+1000	+4500
			PCICLK
		F leads I	ICH2 CLK66 to MCH CLK66	-250	250	-125	+125	-375	+375	8
		Worst-case skew	Worst-case FWHCLK,	-500	+500	-1500	+1500	-2000	+2000	5
		between H, L, M, and	LPCCLK, PCICLK
		N
		B leads D	processor PICCLK leads	-250	+250	-125	+125	-375	+375	6
			processor PICCLK
		B leads G	and
			processor PICCLK leads
			ICH2 APICCLK

NOTES:

1.DP only

2.UP: MCH and processor clock drivers are tied together to eliminate pin-to-pin skew. -175 and +175 pin-to-pin skew apply only to DP.

3.UP only

4.Clock drivers tied together to eliminate pin-to-pin skew.

5.The skew between any PCICLK clocks on any two inputs in the system

6.The skew between any APIC clocks on any two inputs in the system

7.If SSC is enabled, an additional ±40 ps must be added to the pin-to-pin skew.

8.If SSC is enabled, an additional ±60 ps must be added to the pin-to-pin skew.

Design Guide 165