Intel 820E 3.2.1. Initial Timing Analysis

Intel® 820E Chipset
R
142 Design Guide
3.2.1. Initial Timing Analysis
Perform an initial timing analysis of the system using the following two equations, which are the basis for
timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed,
along with the component specifications. These equations contain a multi-bit adjustment factor, MADJ, to
account for multi-bit switching effects (e.g., SSO push-out or pull-in) that often are hard to simulate.
These equations do not take into consideration all signal integrity factors that affect timing. Additional
timing margin should be budgeted to allow for these sources of noise.
Equation 4. Setup Time
TCO_MAX + TSU_MIN + CLKSKEW + CLKJITTER + TFLT_MAX + MADJ ≤ Clock period
Equation 5. Hold Time
TCO_MIN + TFLT_MIN – MADJ ≥ THOLD + CLKSKEW
Symbols used in these two equations:
TCO_MAX Max. clock-to-output specification (see Note)
TSU_MIN Min. required time specified to setup before the clock (see Note)
CLKJITTER Max. clock edge-to-edge variation.
CLKSKEW Max. variation between components receiving the same clock edge
TFLT_MAX Max. flight time, as defined in Section 3.1
TFLT_MIN Min. flight time, as defined in Section 3.1
MADJ Multi-bit adjustment factor to account for SSO push-out or pull-in
TCO_MIN Min. clock-to-output specification (see Note)
THOLD Min. specified input hold time
Note: The clock-to-output (TCO) and setup-to-clock (TSU) timings are both measured from the signal’s last
crossing of VREF, with the requirement that the signal does not violate the ringback or edge rate limits.
See the respective processor’s datasheet and the Pentium® III Processor Developer’s Manual for more
details.
Solving these equations for TFLT yields the following equations:
Equation 6. Maximum Flight Time
TFLT_MAX ≤ Clock period – TCO_MAX – TSU_MIN – CLKSKEW – CLKJITTER – MADJ
Equation 7. Minimum Flight Time
TFLT_MIN ≥ THOLD + CLKSKEW – TCO_MIN + MADJ
Multiple cases must be considered. Note that while the same trace connects two components, component
A and component B, the minimum and maximum flight time requirements for component A driving
component B as well as component B driving component A must be met. The cases to be considered are:
• Processor driving processor
• Processor driving chipset
• Chipset driving processor