Intel 820E manual Differential Clocking/Strobing, Direct RDRAM* Interface, Data Associated Strobe

Intel® 820E Chipset

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Table 2. AGP 2× Data/Strobe Association

Data	Associated Strobe
AD[15:0] and C/BE[1:0]#	AD_STB0
AD[31:16] and C/BE[3:2]#	AD_STB1
SBA[7:0]	SB_STB

In this example, the lower address signals (AD[15:0]) are sampled on the rising and falling edges of AD_STB0, while the upper address signals (AD[31:16]) are sampled on the rising and falling edges of AD_STB1.

When routing strobes and their associated data lines, trace length mismatch is very important, in addition to noise immunity. The primary benefit of source-synchronous strobing is that the data and the strobe arrive simultaneously at the receiver. Thus, a strobe and its associated data signals have very critical length mismatch requirements. With well matched trace lengths (as well as matched impedance), the propagation delays for the strobe and the data will be very close. Hence, the strobe and the data arrive simultaneously at the receiver. For some interfaces, the trace length mismatch requirement is less than

0.25 inch.

2.6.Differential Clocking/Strobing

AGP 2⋅ timings are referenced at a particular level on the rising or falling strobe edge, while 4⋅ timings are referenced to the crossover point of the differential strobes. The crossover is targeted to be at

0.5 VDDQ.

2.7.Direct RDRAM* Interface

The Direct RDRAM channel is a multi-symbol interconnect. Because of the length of the interconnect and the frequency of operation, this bus is designed to allow multiple command and data packets to be present on a signal wire at any given instant. The driving device sends the next data out before the previous data has left the bus.

Figure 12. RIMM Diagram

The nature of the multi-symbol interconnect forces many requirements on the bus design and topology. First and foremost, a drastic reduction in reflected voltage levels is required. The interconnect transmission lines must be terminated at their characteristic impedance, or the reflected voltage resulting from an impedance mismatch will degrade the signal quality. These reflections will reduce noise and timing margins and will reduce the maximum operating frequency of the bus. The reflections could create data errors.

Design Guide 33