Intel® 820E Chipset

R

Figure 81. Layer Switch with Multiple Reference Planes (Same Type)

Signal Layer A

Ground Plane

Layer

Layer

Ground Plane

Signal Layer B

lay_sw_mult_refplane

When routing and stack-up constraints require that an AGTL+ signal reference VCC or multiple planes, special care must be taken to minimize the SSO effect on timing and noise margin. The best method of reducing adverse effects is to add high-frequency decoupling wherever the transitions occur, as shown in the following two figures. Again, such decoupling should be in the vicinity of the signal transition via and should use capacitors with minimal effective series resistance (ESR) and effective series inductance (ESL). When placing the caps, it is advisable to space the VSS and VCC vias as closely as possible and/or use dual vias, since the via inductance may sometimes exceed the actual capacitor inductance.

Figure 82. Layer Switch with Multiple Reference Planes

Signal Layer A

Power Plane

Layer

Layer

Ground Plane

Signal Layer B

lay_sw_mult_refplane

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Design Guide

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Image 158
Intel 820E manual Layer Switch with Multiple Reference Planes Same Type