Cnr | Intel 820E specs

Intel® 820E Chipset

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Figure 52. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade

	Primary	Motherboard	CNR Board
	Primary
	Audio
	Codec
	SDATA_IN
	RESET#
			Audio
			Codec
			RESET#
From AC '97	AC97_RESET#		SDATA_IN
From AC '97	AC97_RESET#		ID0#
Controller
			Vcc
			RB
To General	CDC_DN_ENAB#		100 kΩ
To General	CDC_DN_ENAB#
Purpose Input	RA
	RA
	10 kΩ
To AC '97	SDATA_IN0
To AC '97
Digital	SDATA_IN1
Controller	SDATA_IN1
Controller
			CNR Connector

Figure 52 shows the circuitry required on the motherboard to support a two-codec down configuration. This circuitry disables the codec on a single codec CNR. Notice that in this configuration the resistor, RB, has been changed to 100 kΩ.

Figure 53. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / One-Codec on

CNR

	Primary	Secondary	Motherboard	CNR Board
	Primary	Secondary
	Audio	Codec
	Codec
	SDATA_IN	SDATA_IN
	RESET#	RESET#
				Audio
				Codec
	AC97_RESET#			RESET#
From AC '97				SDATA_IN
From AC '97				ID0#
Controller				ID0#
Controller				Vcc
				Vcc
				RB
To General	CDC_DN_ENAB#			100 kΩ
To General	CDC_DN_ENAB#
Purpose Input	RA
	RA
	10 kΩ
To AC '97	SDATA_IN0
Digital	SDATA_IN1
Controller	SDATA_IN1
Controller
				CNR Connector

Figure 53 shows the case of two-codecs down and a dual-codec CNR. In this case, both codecs on the motherboard are disabled (while both on CNR are active) by RA being 10 kΩ and RB being 1 kΩ.

88	Design Guide

Image 88

Intel 820E manual Cnr

Contents

Intel 820E Chipset Design Guide Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Tables Mil Stack-Up 135 Revision History Rev Description Date Introduction About This Design Guide Reference Documents System Overview Memory Controller Hub MCH Chipset ComponentsController Hub 2 ICH2 FWH Flash Bios Bandwidth SummaryISA Bridge Intel 820E Chipset Platform Bandwidth Summary System Configuration MCH UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Platform Initiatives Direct Rambus RAM RdramStreaming Simd Extensions AGP Integrated LAN Controller Ultra ATA/100 SupportExpanded USB Support Manageability Function Disable Intruder DetectSMBus Interrupt Controller 9. AC’97 C AC’97 Connections Ebga Low-Pin-Count LPC Interface This page is intentionally left blank General Recommendations Component Quadrant Layout MCH Intel 820E Chipset Component Placement Sample ATX and NLX MCH/ICH2 Component Placement Core Chipset Routing Recommendations Primary-Side MCH Core Routing Example ATX Secondary-Side MCH Core Routing Example ATX Source-Synchronous Strobing Data Strobing Example Differential Clocking/Strobing Direct RDRAM* InterfaceAGP 2× Data/Strobe Association Data Associated Strobe Stack-Up Direct RDRAM* Layout Guidelines RSL Routing Placement Guidelines for Motherboard Routing LengthsReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example RSL Termination Direct Rdram Termination Direct RDRAM* Ground Plane Reference Direct RDRAM* Termination Example Plane GND Plane Direct RDRAM* Connector Compensation Equation 1. Approximate Copper Tab Area Calculation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer RSL and Clocking Signal Routing Layer Capacitance pF Section B See Note, Bottom Layer Flood Signal RSL Signal Layer Alternation Length Matching Methods RSL Routing Layer Requirements Equation 2. Rdram RSL Signal Trace Length Calculation Equation 3. Rdram Clock Signal Trace Length Calculation Via Compensation Length Matching and Via Compensation Example Signal Ball on Nominal Package Direct RDRAM* Reference Voltage High-Speed Cmos Routing SIO Routing High-Speed Cmos Termination Suspend-to-RAM Shunt Transistor Rdram Cmos Shunt Transistor Direct RDRAM* Design Checklist Signal ListRSL Signals High-Speed Serial Clocks Direct RDRAM* Clock Routing Intel 820E Chipset If Signal Routed from MCH Primary side AGP Interface Signal Groups AGP Signal Groups 2 × Timing Domain Routing Guidelines 3 ×/4× Timing Domain Routing GuidelinesInterfaces 6 Inches AGP 2.0 Data/Strobe Associations Interfaces 6 Inches and 7.25 Inches AGP 2×/4× Routing Example for Interfaces 6 Inches Signal Maximum Trace Spacing Length Relative To AGP 2.0 Routing SummaryAll AGP Interfaces AGP 2.0 Routing Summary1,2 AGP Clock Routing General AGP Routing GuidelinesRecommendations Decoupling Vddq Generation and TYPEDET# Ground Reference TYPDET#/VDDQ Relationship TYPEDET# on Add-in Card DDQ Supplied by MB Vref Generation for AGP 2.0 2× and 4× AGP Vddq Generation Example Circuit AGP 2.0 Vref Generation and Distribution AGP Pull-Ups Compensation16 k Ω AGP Signal Voltage Tolerance List Connector / Add-in Card InteroperabilityConnector Universal Connector Motherboard / Add-in Card Interoperability AGP Universal Retention Mechanism RM AGP Left-Handed Retention Mechanism AGP Left-Handed RM Keep-Out Information AMP P/N Hub Interface Signal Routing Example Hub Interface Bit Hub Interface Data Signals Bit Hub Interface Strobe SignalsBit Hub Interface Buffer Configuration Setting Bit Hub Interface Routing Guidelines Bit Hub Interface Hubref Generation Circuit Specifications MCH ICH2 Hlrefa Hubref Bit Hub Interface Compensation Bit Hub Interface Decoupling GuidelinesBit Hub Interface Rcomp Resistor Values Component Hub Interface Trace Rcomp Resistor Value System Bus Ground Plane Reference Additional Host Bus GuidelinesMinimizing Crosstalk on the AGTL+ Interface Additional Considerations IDE InterfaceCable Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side Cable Detection Combination Host-Side/Device-Side IDE Cable Detection Device-Side Cable Detection Device-Side IDE Cable Detection Primary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# Sddreq Secondary IDE Connector RequirementsSiordy IRQ15 SDDACK# 13. AC’97 ICH2 AC’97- Codec Connection Intel 820E Chipset Motherboard CNR Board CNR AC97RESET# Signal DescriptionsCDCDNENAB# Valid Codec Configurations Codec ConfigurationsValid Codec Configurations Invalid Codec Configurations 13.3. AC’97 Routing USB Using Native USB InterfaceMotherboard Implementation ISA Support Recommended USB trace characteristicsDisabling the Native USB Interface of ICH2 16. I/O Apic Design Recommendation SMBus/SMLink Interface Pull-Up Requirements for SMBus and SMLink Signals SMBus / SMLink Use Implementation PCI RTC RTC Crystal External Capacitors RTC External Battery Connection RTC Layout Considerations RTC External Rtcrst Circuit Rtcrst External Circuit for ICH2 RTC Spkr Pin Consideration RTC Routing GuidelinesVbias DC Voltage and Noise Measurements RTC-Well Input Strap Requirements ICH2 Pirq Routing Function in ICH2 using the PCI IRQ in IoapicUsage of I/O Apic Interrupt Inputs 16 through LAN Connect Component Connection Features LAN Layout GuidelinesPIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd LAN Design Guide Section Reference ICH2 LAN Interconnect GuidelinesLayout Section Previous Design Guide Section Point-to-Point Interconnect Bus TopologiesLOM/CNR Interconnect Configuration Signal Routing and LayoutLength Requirements for Figure Impedances Crosstalk ConsiderationLine Termination General LAN Routing Guidelines and Considerations General Trace Routing Considerations Power and Ground Connections Trace Geometry and Length Ground Plane Separation Layer Board Design Design Guide 111 Guidelines for Intel 82562EH Component Placement Intel 82562EH Home/PNA* GuidelinesCrystals and Oscillators Related Documents Phoneline Hpna Termination Intel 82562EH Component Termination Critical Dimensions LPFEeprom Distance Priority Guideline Intel 82562ET / Intel 82562EM Component Guidelines Distance from LPF to Phone RJ11 Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Reducing Circuit Inductance Terminating Unused Connections Intel 82562ET/EM Disable Guidelines LAN Disable Circuit Lancl Dual-Footprint Analog Interface ICH2 Decoupling Recommendations Power Plane/Pins # Decoupling Capacitor ValueDecoupling Capacitor Recommendation Decoupling Capacitor Layout In-Circuit FWH Flash Bios Programming FWH Flash Bios GuidelinesFWH Flash Bios VPP Design Guidelines Checklist Items Recommendations Reason/Effect ICH2 Design ChecklistPCI Interface FWH Flash Bios Interface Hub InterfaceLAN Interface Eeprom Interface Interrupt Interface PIRQ#DAPIRQ#H PIRQ#E USB Interface GpioVCCSUS3.3 Processor Signals RTC System ManagementAC’97 Miscellaneous Signals PowerSpkr 5VREF SUS IDE Checklist Checklist Items ISA Bridge ChecklistICH2 AD22 / ISA ICH2 Layout Checklist Bit Hub InterfaceIDE Interface USB LAN Connect I/F ICH2 Decoupling CK-SKS Clocking Layout Recommendations Yes 138 Design Guide Terminology and Definitions Term Definition 140 Design Guide AGTL+ Design Guidelines Guideline Methodology Equation 4. Setup Time Initial Timing AnalysisEquation 5. Hold Time Equation 6. Maximum Flight Time AGTL+ Parameters for Example Calculations1,2 IC Parameters Pentium Intel Example Tfltmax Calculations for 133 MHz Bus1 Driver Receiver Clk Determine the Desired General Topology, Layout, and Routing Pre-Layout SimulationMethodology Sensitivity Analysis Monte Carlo Analysis Simulation Criteria Place and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsLayout and Route Board Trace Width Space Guidelines Host Clock Routing Apic Data Bus RoutingCrosstalk Type Trace WidthSpace Ratio Intersymbol Interference Post-Layout Simulation Crosstalk Analysis ValidationMeasurements Flight Time Simulation Flight Time Hardware Validation Equation 8. Valid Delay EquationSET Q CLR Q AGTL+ TheoryTiming Requirements Crosstalk Theory Aggressor and Victim Networks Potential Termination Crosstalk Problems More Details and Insight Textbook Timing Equations Power Distribution Effective Impedance and Tolerance/Variation One Signal Layer and One Reference Plane Reference Planes and PCB Stack-Up Layer Switch with Multiple Reference Planes Same Type High-Frequency Decoupling One Layer with Multiple Reference Planes Clock Routing Ringback Levels Vref Guard BandOverdrive Region Conclusion Flight Time Definition and Measurement Intel 820E Chipset Platform System Clocks Clock GenerationNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Platform Clock SkewsLPCCLK, Pciclk Intel 820E Chipset Clock Routing Guidelines1,2 ±TBD3 Intel 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component 1 .318 MHz Crystal to CK133 Component Placement and Interconnection Layout Requirements2. CK133 to Drcg MCH-to-DRCG Routing Diagram MCH to Drcg DRCG-to-RDRAM Channel Trace LengthTrace Geometry Clock From Length inches Section Differential Clock Routing Diagram Sections A, C & D Drcg Impedance Matching Circuit External Drcg Component Values1,2Component Nominal Value CMID, CMID2 AGP Clock Routing Guidelines Clock Routing Guidelines for Intel PGA370 DesignsSeries Termination Resistors for CK133 Clock Outputs Drcg Layout Example Unused Outputs Decoupling Recommendation for CK133 and DrcgUnused Output Termination Buffer Name CC Range Impedance If Unused Output Drcg Frequency Selection Table and Jitter Specification Drcg Frequency Selection and the DRCG+ DRCG+ Frequency Selection Schematic DRCG+ Frequency Selection Stack-Up Requirement PCB Materials Design Process Test Coupon Design Guidelines Recommended Stack-Up Inner-Layer RoutingStack-Up Examples Sample SM max Resin % Impedance Calculation Tools Field Solver vs. Zcalc Testing Board Impedance Board Impedance/Stack-up Summary 182 Design Guide Terminology and Definitions Power DeliveryTerm Definition Intel 820E Chipset Power Delivery Example Dual Switch VCC Vbsy V and 2.5 V Power Sequencing Schottky Diode 3VSB ICH2 1.8 V / 3.3 V Power Sequencing VSB Example 1.8V/3.3V Power Sequencing Circuit 4 .3V/V5REF Sequencing Option 1 Reduce the Clock Frequency During Initialization Excessive Power Consumption by 64/72-Mbit RdramVref Use a GPO to Reduce Drcg Frequency ICH2 Power Plane Split Example of ICH2 Power Plane Split Thermal Design Power FeaturesIntel 820E Chipset Component Thermal Design Power Component Thermal Design Power 133/400 MHz Glue Chip Vendors Vendor Intel Contact Contact Information Appendix a Reference Design Schematics Uniprocessor Reference Design Feature Set 196 Design Guide REV Drawn by PCG Platform Design Project PCG AEPrairie City Road FOLSOM, California Last Revised Sheet Block Diagram Device Table AK8 AH8AN9 AL9 CPURST#R2 DBRESET# VCMOS15Gtlref Tckr TDI Tmsr Clock Synthesizer Hubref Ramrefr RamrefConnagpref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host GAD0 GAD0 GAD1GAD1 GAD2 GAD2 GAD3 AD0 AD1AD2 AD3 ACRESET# CR4Vbatcr 1UF Rtcrstjp NC1 Gnda Fwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 SWP RSRV4/RESET RSRV4/RESET SWPTERMDQA80 Rimm LDQA0 Super I/O AC’97 Audio Micinr Micinfb MicinMicinc DB15AUDSTK Communication And Network Riser CNR Stubs on AC97 Link ACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2RP7 ACSDATAIN0CNR Acsynccnr Acsdataoutcnr LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH H1138ARAGONITE LAN RJ45 For 82562ET/EMLanactled 25MHZ Y5 Xtal Y2 Xtal LANCLKX1R381LANCLKX2 LAN Option Intel PART# Stuff for 82562EH Power SW Power LEDSW1 VCC12 Irtx AGP4XU20 AGPOC# TYPEDET#USBAGP+ B4 Usbagp Agpclkconn B7 CLK VCC5 VCC12 PCI3CON PTRST# PtckPtms Ptdi PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy Game Port VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr VRM Fault VRM IFB FAULT# IFBVccvid REV Project Imax VRM G1 VRM G2 Voltage Regulators 1UF-X7R VCC33SBYTG VCC33SBYSW VCC25SBYVCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH SBY ITH R Power Connector BPRI# DBSY# HREQ#0 PCI/AGP Pullups/Pulldowns Rambus* Termination Termcmd Termsck Decoupling VCMOS18SBY Bulk Decoupling Drawn by PCG Platform Design Project PCG AE Revision History Revision History Drawn by PCG Platform Design Project PCG AE Hub Interface Connector For debug only Probe ConnectorTESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# HL8 HL4 HL5 HL6 HL7