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Intel 820E manual UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs

Models: 820E

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Intel® 820E Chipset

R

Figure 3. Intel® 820E Chipset Platform Dual-Processor Performance Desktop Block Diagram

Intel® Pentium® III

Processor

Intel® Pentium® III

Processor

Intel® 820E Chipset

4x AGP		AGP 2.0
4x AGP
Graphics
Controller

	4 IDE Drives
UltraATA/100/66/33
4 USB Ports; 2 HC
AC'97 Codec(s)		AC'97 2.1
	(optional)
	LAN Connect
Other ASICs	Super I/O
(optional)	Super I/O
(optional)
		LPC I/F

	Intel®	Main
	82820 Memory	Main
	82820 Memory	Memory
	Controller Hub	Memory
	Controller Hub	(Direct RDRAM*)
	(MCH)	(Direct RDRAM*)
	(MCH)
	Hub
	Interface
		PCI
		Slots
		PCI Bus
	I/O Controller Hub	Power Management
	Intel® 82801BA	Power Management
	Intel® 82801BA
	(ICH2)
		Clock Generators
		System Management (TCO)
		SMBus/I2C
		GPIO
	FWH Flash
	BIOS
		sys_blk_2P_820E

Design Guide

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Image 19

Intel 820E manual UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs

Contents

Design Guide Intel 820E ChipsetIntel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Mil Stack-Up Tables135 Rev Description Date Revision HistoryAbout This Design Guide IntroductionReference Documents System Overview Memory Controller Hub MCH Chipset ComponentsController Hub 2 ICH2 Intel 820E Chipset Platform Bandwidth Summary FWH Flash BiosBandwidth Summary ISA BridgeMCH System ConfigurationUltraATA/100/66/33 USB Ports 2 HC AC97 Codecs AGP Platform InitiativesDirect Rambus RAM Rdram Streaming Simd ExtensionsManageability Integrated LAN ControllerUltra ATA/100 Support Expanded USB SupportInterrupt Controller Function DisableIntruder Detect SMBus9. AC’97 Ebga C AC’97 ConnectionsLow-Pin-Count LPC Interface This page is intentionally left blank Component Quadrant Layout General RecommendationsMCH Sample ATX and NLX MCH/ICH2 Component Placement Intel 820E Chipset Component PlacementPrimary-Side MCH Core Routing Example ATX Core Chipset Routing RecommendationsSecondary-Side MCH Core Routing Example ATX Data Strobing Example Source-Synchronous StrobingData Associated Strobe Differential Clocking/StrobingDirect RDRAM* Interface AGP 2× Data/Strobe AssociationDirect RDRAM* Layout Guidelines Stack-UpRSL Routing Placement Guidelines for Motherboard Routing LengthsReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example Direct Rdram Termination RSL TerminationDirect RDRAM* Termination Example Direct RDRAM* Ground Plane ReferenceGND Plane PlaneEquation 1. Approximate Copper Tab Area Calculation Direct RDRAM* Connector CompensationCopper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer Section B See Note, Bottom Layer RSL and Clocking Signal Routing Layer Capacitance pFFlood Signal RSL Signal Layer Alternation RSL Routing Layer Requirements Length Matching MethodsEquation 3. Rdram Clock Signal Trace Length Calculation Equation 2. Rdram RSL Signal Trace Length CalculationLength Matching and Via Compensation Example Via CompensationSignal Ball on Nominal Package High-Speed Cmos Routing Direct RDRAM* Reference VoltageHigh-Speed Cmos Termination SIO RoutingRdram Cmos Shunt Transistor Suspend-to-RAM Shunt TransistorDirect RDRAM* Clock Routing Direct RDRAM* Design ChecklistSignal List RSL Signals High-Speed Serial ClocksIntel 820E Chipset Primary side If Signal Routed from MCHAGP AGP Interface Signal GroupsSignal Groups AGP 2.0 Data/Strobe Associations 2 × Timing Domain Routing Guidelines3 ×/4× Timing Domain Routing Guidelines Interfaces 6 InchesAGP 2×/4× Routing Example for Interfaces 6 Inches Interfaces 6 Inches and 7.25 InchesAGP 2.0 Routing Summary1,2 Signal Maximum Trace Spacing Length Relative ToAGP 2.0 Routing Summary All AGP InterfacesDecoupling AGP Clock RoutingGeneral AGP Routing Guidelines RecommendationsGround Reference Vddq Generation and TYPEDET#TYPEDET# on Add-in Card DDQ Supplied by MB TYPDET#/VDDQ RelationshipAGP Vddq Generation Example Circuit Vref Generation for AGP 2.0 2× and 4×AGP 2.0 Vref Generation and Distribution AGP Pull-Ups Compensation16 k Ω Motherboard / Add-in Card Interoperability AGP Signal Voltage Tolerance ListConnector / Add-in Card Interoperability Connector Universal ConnectorAGP Left-Handed Retention Mechanism AGP Universal Retention Mechanism RMAMP P/N AGP Left-Handed RM Keep-Out InformationHub Interface Hub Interface Signal Routing ExampleBit Hub Interface Routing Guidelines Bit Hub Interface Data SignalsBit Hub Interface Strobe Signals Bit Hub Interface Buffer Configuration SettingMCH ICH2 Hlrefa Hubref Bit Hub Interface Hubref Generation Circuit SpecificationsComponent Hub Interface Trace Rcomp Resistor Value Bit Hub Interface CompensationBit Hub Interface Decoupling Guidelines Bit Hub Interface Rcomp Resistor ValuesSystem Bus Ground Plane Reference Additional Host Bus GuidelinesMinimizing Crosstalk on the AGTL+ Interface Additional Considerations IDE InterfaceCable Combination Host-Side/Device-Side Cable Detection Cable Detection for Ultra ATA/66 and Ultra ATA/100Combination Host-Side/Device-Side IDE Cable Detection Device-Side IDE Cable Detection Device-Side Cable DetectionPrimary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# Sddreq Secondary IDE Connector RequirementsSiordy IRQ15 SDDACK# ICH2 AC’97- Codec Connection 13. AC’97Intel 820E Chipset Motherboard CNR Board CNR AC97RESET# Signal DescriptionsCDCDNENAB# Invalid Codec Configurations Valid Codec ConfigurationsCodec Configurations Valid Codec Configurations13.3. AC’97 Routing USB Using Native USB InterfaceMotherboard Implementation ISA Support Recommended USB trace characteristicsDisabling the Native USB Interface of ICH2 SMBus/SMLink Interface 16. I/O Apic Design RecommendationSMBus / SMLink Use Implementation Pull-Up Requirements for SMBus and SMLink SignalsRTC PCIExternal Capacitors RTC CrystalRTC Layout Considerations RTC External Battery ConnectionRtcrst External Circuit for ICH2 RTC RTC External Rtcrst CircuitRTC-Well Input Strap Requirements Spkr Pin ConsiderationRTC Routing Guidelines Vbias DC Voltage and Noise MeasurementsICH2 Pirq Routing Function in ICH2 using the PCI IRQ in IoapicUsage of I/O Apic Interrupt Inputs 16 through PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd LAN Connect Component Connection FeaturesLAN Layout Guidelines PIRQA# PIRQB# PIRQC# PIRQD#LAN Design Guide Section Reference ICH2 LAN Interconnect GuidelinesLayout Section Previous Design Guide Section Point-to-Point Interconnect Bus TopologiesLOM/CNR Interconnect Configuration Signal Routing and LayoutLength Requirements for Figure Impedances Crosstalk ConsiderationLine Termination General Trace Routing Considerations General LAN Routing Guidelines and ConsiderationsTrace Geometry and Length Power and Ground ConnectionsGround Plane Separation Layer Board Design Design Guide 111 Related Documents Guidelines for Intel 82562EH Component PlacementIntel 82562EH Home/PNA* Guidelines Crystals and OscillatorsIntel 82562EH Component Termination Phoneline Hpna TerminationDistance Priority Guideline Critical DimensionsLPF EepromDistance from LPF to Phone RJ11 Intel 82562ET / Intel 82562EM Component GuidelinesIntel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Terminating Unused Connections Reducing Circuit InductanceLAN Disable Circuit Intel 82562ET/EM Disable GuidelinesLancl Dual-Footprint Analog Interface ICH2 Decoupling Recommendations Power Plane/Pins # Decoupling Capacitor ValueDecoupling Capacitor Recommendation Decoupling Capacitor Layout In-Circuit FWH Flash Bios Programming FWH Flash Bios GuidelinesFWH Flash Bios VPP Design Guidelines Checklist Items Recommendations Reason/Effect ICH2 Design ChecklistPCI Interface Eeprom Interface FWH Flash Bios InterfaceHub Interface LAN InterfacePIRQ#E Interrupt InterfacePIRQ#DA PIRQ#HUSB Interface GpioVCCSUS3.3 Processor Signals RTC System ManagementAC’97 5VREF SUS Miscellaneous SignalsPower SpkrIDE Checklist Checklist Items ISA Bridge ChecklistICH2 AD22 / ISA USB ICH2 Layout ChecklistBit Hub Interface IDE InterfaceLAN Connect I/F ICH2 Decoupling Layout Recommendations Yes CK-SKS Clocking138 Design Guide Term Definition Terminology and Definitions140 Design Guide Guideline Methodology AGTL+ Design GuidelinesEquation 6. Maximum Flight Time Equation 4. Setup TimeInitial Timing Analysis Equation 5. Hold TimeIC Parameters Pentium Intel AGTL+ Parameters for Example Calculations1,2Driver Receiver Clk Example Tfltmax Calculations for 133 MHz Bus1Sensitivity Analysis Determine the Desired General Topology, Layout, and RoutingPre-Layout Simulation MethodologySimulation Criteria Monte Carlo AnalysisPlace and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsLayout and Route Board Trace Width Space Guidelines Host Clock Routing Apic Data Bus RoutingCrosstalk Type Trace WidthSpace Ratio Post-Layout Simulation Intersymbol InterferenceCrosstalk Analysis ValidationMeasurements Flight Time Simulation Flight Time Hardware Validation Equation 8. Valid Delay EquationSET Q CLR Q AGTL+ TheoryTiming Requirements Aggressor and Victim Networks Crosstalk TheoryPotential Termination Crosstalk Problems Textbook Timing Equations More Details and InsightEffective Impedance and Tolerance/Variation Power DistributionReference Planes and PCB Stack-Up One Signal Layer and One Reference PlaneLayer Switch with Multiple Reference Planes Same Type One Layer with Multiple Reference Planes High-Frequency DecouplingClock Routing Ringback Levels Vref Guard BandOverdrive Region Flight Time Definition and Measurement ConclusionIntel 820E Chipset Platform System Clocks Clock GenerationNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Platform Clock SkewsLPCCLK, Pciclk ±TBD3 Intel 820E Chipset Clock Routing Guidelines1,2CK133/DRCG Pin Name Component Intel 820E Chipset Platform System Clock Cross-Reference1 .318 MHz Crystal to CK133 Component Placement and Interconnection Layout Requirements2. CK133 to Drcg MCH to Drcg MCH-to-DRCG Routing DiagramClock From Length inches Section DRCG-to-RDRAM ChannelTrace Length Trace GeometryDifferential Clock Routing Diagram Sections A, C & D CMID, CMID2 Drcg Impedance Matching CircuitExternal Drcg Component Values1,2 Component Nominal ValueDrcg Layout Example AGP Clock Routing GuidelinesClock Routing Guidelines for Intel PGA370 Designs Series Termination Resistors for CK133 Clock OutputsBuffer Name CC Range Impedance If Unused Output Unused OutputsDecoupling Recommendation for CK133 and Drcg Unused Output TerminationDrcg Frequency Selection and the DRCG+ Drcg Frequency Selection Table and Jitter SpecificationDRCG+ Frequency Selection DRCG+ Frequency Selection SchematicPCB Materials Stack-Up RequirementTest Coupon Design Guidelines Design ProcessSample SM max Resin % Recommended Stack-UpInner-Layer Routing Stack-Up ExamplesField Solver vs. Zcalc Impedance Calculation ToolsBoard Impedance/Stack-up Summary Testing Board Impedance182 Design Guide Terminology and Definitions Power DeliveryTerm Definition Intel 820E Chipset Power Delivery Example VCC Dual SwitchVbsy 3VSB V and 2.5 V Power Sequencing Schottky DiodeVSB ICH2 1.8 V / 3.3 V Power Sequencing4 .3V/V5REF Sequencing Example 1.8V/3.3V Power Sequencing CircuitOption 1 Reduce the Clock Frequency During Initialization Excessive Power Consumption by 64/72-Mbit RdramVref Use a GPO to Reduce Drcg Frequency Example of ICH2 Power Plane Split ICH2 Power Plane SplitComponent Thermal Design Power 133/400 MHz Thermal Design PowerFeatures Intel 820E Chipset Component Thermal Design PowerVendor Intel Contact Contact Information Glue Chip VendorsReference Design Feature Set Appendix a Reference Design Schematics Uniprocessor196 Design Guide FOLSOM, California Last Revised Sheet REVDrawn by PCG Platform Design Project PCG AE Prairie City RoadDevice Table Block DiagramAL9 AK8AH8 AN9Tckr TDI Tmsr CPURST#R2 DBRESET#VCMOS15 GtlrefClock Synthesizer Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host Hubref RamrefrRamref ConnagprefGAD2 GAD3 GAD0GAD0 GAD1 GAD1 GAD2AD3 AD0AD1 AD2Rtcrstjp ACRESET#CR4 Vbatcr 1UFVCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 NC1 GndaFwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32Rimm LDQA0 SWP RSRV4/RESETRSRV4/RESET SWP TERMDQA80Super I/O AC’97 Audio DB15AUDSTK Micinr MicinfbMicin MicincCommunication And Network Riser CNR ACSDATAIN0CNR Acsynccnr Acsdataoutcnr Stubs on AC97 LinkACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 RP7LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH H1138ARAGONITE LAN RJ45 For 82562ET/EMLanactled LAN Option Intel PART# 25MHZY5 Xtal Y2 Xtal LANCLKX1 R381LANCLKX2Stuff for 82562EH VCC12 Irtx Power SWPower LED SW1Agpclkconn B7 CLK AGP4XU20 AGPOC#TYPEDET# USBAGP+ B4 UsbagpPtdi VCC5 VCC12PCI3CON PTRST# Ptck PtmsPCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Game PortImax VRM G1 VRM G2 VRM Fault VRM IFBFAULT# IFB Vccvid REV ProjectVoltage Regulators SBY ITH R 1UF-X7RVCC33SBYTG VCC33SBYSW VCC25SBY VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITHPower Connector HREQ#0 BPRI# DBSY#PCI/AGP Pullups/Pulldowns Termcmd Termsck Rambus* TerminationDecoupling Bulk Decoupling Drawn by PCG Platform Design Project PCG AE VCMOS18SBYRevision History Drawn by PCG Platform Design Project PCG AE Revision HistoryHL8 HL4 HL5 HL6 HL7 Hub Interface Connector For debug onlyProbe Connector TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB#