Intel® 820E Chipset

R

Figure 54. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / Two-Codecs on

CNR

 

Codec A

Codec B

Motherboard

CNR Board

 

 

 

 

 

 

SDATA_IN

SDATA_IN

 

 

 

 

 

 

 

 

 

 

 

RESET#

RESET#

 

 

 

 

 

 

 

 

 

 

Codec C

 

 

 

 

 

 

RESET#

From AC '97

AC97_RESET#

 

 

 

 

SDATA_IN

Controller

 

 

 

 

 

 

 

 

 

 

Vcc

 

Codec D

 

 

 

 

RB

 

To General

CDC_DN_ENAB#

 

 

 

RESET#

 

 

1

κΩ

SDATA_IN

Purpose Input

RA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 k

 

 

 

 

 

To AC '97

SDATA_IN0

 

 

 

 

 

Digital

SDATA_IN1

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CNR Connector

Circuit Notes

1.While it is possible to disable down codecs, as shown above in Figure 53 and Figure 54, it is recommended against for reasons cited in the ICHx/AC'97 White Paper, including avoidance of shipping redundant and/or non-functional audio jacks.

2.All CNR designs include resistor RB. The value of RB is either 1 kΩ or 100 kΩ, depending on the intended functionality of the CNR (whether or not it intends to be the primary/controlling codec).

3.Any CNR with two codecs must implement RB with value 1 kΩ. If there is one codec, use a

100 kΩ pull-up resistor. A CNR with zero codecs must not stuff RB. If implemented, RB must be connected to the same power well as the codec so that it is valid whenever the codec has power.

4.A motherboard with one or more codecs down must implement RA with a value of 10 kΩ.

5.The CDC_DN_ENAB# signal must be run to a GPI so that the BIOS can sense the state of the signal. CDC_DN_ENAB# is required to be connected to a GPI; a connection to a GPIO is strongly recommended for testing purposes.

Table 18. Signal Descriptions

CDC_DN_ENAB#

When low, indicates that the codec on the motherboard is enabled and

 

primary on the AC’97 Interface. When high, indicates that the motherboard

 

codec(s) must be removed from the AC’97 Interface (held in reset), because

 

the CNR codec(s) will be the primary device(s) on the AC’97 Interface.

 

 

AC97_RESET#

Reset signal from the AC’97 Digital Controller (ICH2).

 

 

SDATA_INn

AC’97 serial data from an AC’97-compliant codec to an AC’97-compliant

 

controller (i.e., the ICH2).

 

 

Design Guide

89

Page 89
Image 89
Intel 820E manual Signal Descriptions, Cdcdnenab#, AC97RESET#