Intel 820E 3.2.3.3. Monte Carlo Analysis , 3.2.3.4. Simulation Criteria

Intel® 820E Chipset
R
146 Design Guide
3.2.3.3. Monte Carlo Analysis
Perform a Monte Carlo Analysis to refine the passing solution space region. A Monte Carlo Analysis
involves randomly varying parameters independently of one another, over their tolerance ranges. This
analysis is designed to ensure that no region of failing flight time and signal quality exists between the
extreme corner cases run in pre-layout simulations. For the example topology, vary the following
parameters during Monte Carlo simulations:
• Lengths L1 through L3
• Termination resistance RTT on processor Intel PGA370 socket 1
• Termination resistance RTT on processor Intel PGA370 socket 2
• Z0 of traces on processor Intel PGA370 socket 1
• Z0 of traces on processor Intel PGA370 socket 2
• S0 of traces on processor Intel PGA370 socket 1
• S0 of traces on processor Intel PGA370 socket 2
• Z0 of traces on baseboard
• S0 of traces on baseboard
• Fast and slow corner processor I/O buffer models for Intel PGA370 socket 1
• Fast and slow corner processor I/O buffer models for Intel PGA370 socket 2
• Fast and slow package models for processor Intel PGA370 socket 1
• Fast and slow package models for processor Intel PGA370 socket 2
• Fast and slow corner Intel 82820 MCH I/O buffer models
• Fast and slow Intel 82820 MCH package models
3.2.3.4. Simulation Criteria
Accurate simulation requires that the actual range of parameters be used in the simulation. Intel has
consistently measured the cross-sectional resistivity of PCB copper to be approximately 1 Ω⋅mil2/inch,
not the 0.662 Ω⋅mil2/inch value for annealed copper that is published in reference material. Using the
1 Ω⋅mil2/inch value may increase the accuracy of lossy simulations.
Positioning drivers with faster edges closer to the middle of the network typically results in more noise
than positioning them towards the ends. However, Intel has shown that drivers located in all positions—
given appropriate variations in the other network parameters—can generate the worst-case noise margin.
Therefore, Intel recommends simulating the networks from all driver locations and analyzing each
receiver for each possible driver.
Analysis has shown that both fast and slow corner conditions must be run for both rising-edge and
falling-edge transitions. The fast corner is needed because the fast edge rate creates the most noise. The
slow corner is needed because the buffer’s drive capability will be minimum, causing the VOL to shift up,
which may cause the noise from the slower edge to exceed the available budget. Slow corner models may
produce minimum flight time violations on rising edges if the transition starts from a higher VOL. So,
Intel highly recommends checking for minimum and maximum flight time violations with both the fast
and slow corner models. The fast and slow corner I/O buffer models are contained in the processor and
Intel 820 chipset electronic models provided by Intel.