Intel® 820E Chipset

R

2.12.5.Secondary IDE Connector Requirements

Figure 49. Connection Requirements for Secondary IDE Connector

 

PCIRST_BUF#

22–47

 

PCIRST# *

 

 

Reset#

SDD[15:0]

 

 

 

SDA[2:0]

 

 

 

SDCS1#

 

 

 

SDCS3#

 

 

 

SDIOR#

 

 

 

SDIOW#

 

 

 

SDDREQ

3.3 V

 

 

 

 

 

 

3.3 V

 

 

4.7 k

8.2–10 k

 

Secondary IDE

 

 

 

 

 

Connector

SIORDY

 

 

 

IRQ15

 

 

 

SDDACK#

 

 

 

GPIOy

 

 

PDIAG# / CBLID#

 

10 k

 

CSEL

 

 

 

ICH2

 

N.C.

Pins 32 & 34

 

 

 

*Due to ringing, PCIRST# must be buffered.

NOTES:

IDE_secondary_conn_require

1.

22 to 47 series resistors are required on RESET#. The correct value should be determined for each

 

unique motherboard design, based on the signal quality.

2.

An 8.2 kto 10 kpull-up resistor is required on IRQ14 and IRQ15 to VCC3.

3.A 4.7 kpull-up resistor to VCC3 is required on PIORDY and SIORDY

4.Series resistors can be placed on the control and data lines to improve signal quality. The resistors are place as close as possible to the connector. Values are determined for each unique motherboard design.

5.A 10 kpull-down resistor to ground is required on the PDIAG/CBLID signal. This prevents the GPI pin from floating if a device is not present on the secondary IDE interface.

84

Design Guide

Page 84
Image 84
Intel 820E manual Secondary IDE Connector Requirements, SDCS1# SDCS3# SDIOR# SDIOW# Sddreq, Siordy IRQ15 SDDACK#