Intel 820E manual 191

Intel® 820E Chipset

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	4.8.	Decoupling Recommendation for CK133 and DRCG			174
	4.9.	DRCG Frequency Selection and the DRCG+			175
		4.9.1.	DRCG Frequency Selection Table and Jitter Specification		175
		4.9.2.	DRCG+ Frequency Selection Schematic		176
5.	System Manufacturing				177
	5.1.	Stack-Up Requirement			177
		5.1.1.	PCB Materials		177
		5.1.2.	Design Process		178
		5.1.3.	Test Coupon Design Guidelines		178
		5.1.4.	Recommended Stack-Up		179
		5.1.5.	Inner-Layer Routing		179
		5.1.6.	Impedance Calculation Tools		180
		5.1.7.	Testing Board Impedance		181
		5.1.8.	Board Impedance/Stack-up Summary		181
6.	System Design Considerations				183
	6.1.	Power Delivery			183
		6.1.1.	Terminology and Definitions		183
		6.1.2.	Power Delivery of Intel® 820E Chipset Customer Reference Board		184
		6.1.3.	ICH2 1.8 V / 3.3 V Power Sequencing		188
		6.1.5.	Excessive Power Consumption by 64/72-Mbit RDRAM		190
			6.1.5.1.	Option 1: Reduce the Clock Frequency During Initialization	190
			6.1.5.2.	Option 2: Increase the Current Capability of the 2.5 V Voltage
				Regulator	191
	6.2.	ICH2 Power Plane Split			192
	6.3.	Thermal Design Power			193
	6.4.	Glue Chip 3 (Intel® 820E Chipset Glue Chip)			193
Appendix A: Reference Design Schematics (Uniprocessor)					195

Design Guide 7