25MHZ, Y5 Xtal Y2 Xtal LANCLKX1, R381LANCLKX2 | Intel 820E specification

8

7

6

5

4

3

2

1

LAN

D

	C291
		82PF
		5%
		1
		25MHZ



	C302	2
	C302	82PF
		82PF
		5%

	20MHZ	1
Y5 XTAL	20MHZ	Y2 XTAL
		2

LAN_CLK_X1

17,18

R382	10K
	10K
	1%

R381LAN_CLK_X2

17,18

121

1%

D

C

S t u f f i n g O p t i o n s f o r 8 2 5 6 2 E H a n d 8 2 5 6 2 E T / E M


82562EH	R e m o ve		Y 5
	C 2 9 1	a n d		C 3 0 2 = 8 2 p f
	R 3 8 1 = 1 2 1 o h m s
82562ET/EM	R e m o ve		Y 2
	C 2 9 1	a n d		C 3 0 2 = 2 2 p f
	R 3 8 1 = 0		o h m s
	R e m o ve		R	3 8 2

9,15

9,15

9,15

15

			VCC3_3SBY
			U22
			93C46	8
	EE_DOUT_ICH2	3	VCC
	EE_DIN_ICH2	4	EEDI		7
	EE_DIN_ICH2	4	EEDO	NC2	7
	EE_SHCLK_ICH2	2	EEDO	NC2	6
	EE_SHCLK_ICH2	2	EESK	NC1	6
	EE_CS_ICH2_OB	1	EESK	NC1
	EE_CS_ICH2_OB	1	EECS
			EECS

GND 5

C

B

A

STUFF FOR 82562EH ONLY

GILAD_RDP			R377
17			0K
			0K
VCC3_3SBY	R376	51.1	R379
VCC3_3SBY		51.1
		1%
		1%	806
			806
	R95		1%
	R95
	806		C365
	1%
	R378		0.022UF
	R378	51.1	10%
		51.1
		1%
GILAD_RDM			R380
17			0K
			0K

LAN_RDP

18,19,20

LAN_RDM

18,19,20

STUFFING FOR EEPROM (U22)

LAN OPTION	INTEL PART#
82562EH	A05482-001
82562ET	A05441-001
82562EM	A05723-001
82562EM with AOL

B

A

8

7

6

5

4

	TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD					REV:
	LAN				DRAWN BY:	0.5
			R	PCG PLATFORM DESIGN	DRAWN BY:	PROJECT:
			R	PCG PLATFORM DESIGN	PCG AE	Camino2
				1900 PRAIRIE CITY ROAD	PCG AE	Camino2
				FOLSOM, CALIFORNIA 95630	LAST REVISED:	SHEET:
				FOLSOM, CALIFORNIA 95630	3-20-2000_11:31	21 OF 40
					3-20-2000_11:31	21 OF 40
3				2	1

Image 217

Intel 820E manual 25MHZ, Y5 Xtal Y2 Xtal LANCLKX1, R381LANCLKX2, LAN Option Intel PART#

Contents

Design Guide Intel 820E Chipset Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Mil Stack-Up Tables 135 Rev Description Date Revision History About This Design Guide Introduction Reference Documents System Overview Memory Controller Hub MCH Chipset ComponentsController Hub 2 ICH2 Bandwidth Summary FWH Flash BiosISA Bridge Intel 820E Chipset Platform Bandwidth Summary MCH System Configuration UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Direct Rambus RAM Rdram Platform InitiativesStreaming Simd Extensions AGP Ultra ATA/100 Support Integrated LAN ControllerExpanded USB Support Manageability Intruder Detect Function DisableSMBus Interrupt Controller 9. AC’97 Ebga C AC’97 Connections Low-Pin-Count LPC Interface This page is intentionally left blank Component Quadrant Layout General Recommendations MCH Sample ATX and NLX MCH/ICH2 Component Placement Intel 820E Chipset Component Placement Primary-Side MCH Core Routing Example ATX Core Chipset Routing Recommendations Secondary-Side MCH Core Routing Example ATX Data Strobing Example Source-Synchronous Strobing Direct RDRAM* Interface Differential Clocking/StrobingAGP 2× Data/Strobe Association Data Associated Strobe Direct RDRAM* Layout Guidelines Stack-Up RSL Routing Placement Guidelines for Motherboard Routing LengthsReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example Direct Rdram Termination RSL Termination Direct RDRAM* Termination Example Direct RDRAM* Ground Plane Reference GND Plane Plane Equation 1. Approximate Copper Tab Area Calculation Direct RDRAM* Connector Compensation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer Section B See Note, Bottom Layer RSL and Clocking Signal Routing Layer Capacitance pF Flood Signal RSL Signal Layer Alternation RSL Routing Layer Requirements Length Matching Methods Equation 3. Rdram Clock Signal Trace Length Calculation Equation 2. Rdram RSL Signal Trace Length Calculation Length Matching and Via Compensation Example Via Compensation Signal Ball on Nominal Package High-Speed Cmos Routing Direct RDRAM* Reference Voltage High-Speed Cmos Termination SIO Routing Rdram Cmos Shunt Transistor Suspend-to-RAM Shunt Transistor Signal List Direct RDRAM* Design ChecklistRSL Signals High-Speed Serial Clocks Direct RDRAM* Clock Routing Intel 820E Chipset Primary side If Signal Routed from MCH AGP AGP Interface Signal Groups Signal Groups 3 ×/4× Timing Domain Routing Guidelines 2 × Timing Domain Routing GuidelinesInterfaces 6 Inches AGP 2.0 Data/Strobe Associations AGP 2×/4× Routing Example for Interfaces 6 Inches Interfaces 6 Inches and 7.25 Inches AGP 2.0 Routing Summary Signal Maximum Trace Spacing Length Relative ToAll AGP Interfaces AGP 2.0 Routing Summary1,2 General AGP Routing Guidelines AGP Clock RoutingRecommendations Decoupling Ground Reference Vddq Generation and TYPEDET# TYPEDET# on Add-in Card DDQ Supplied by MB TYPDET#/VDDQ Relationship AGP Vddq Generation Example Circuit Vref Generation for AGP 2.0 2× and 4× AGP 2.0 Vref Generation and Distribution AGP Pull-Ups Compensation16 k Ω Connector / Add-in Card Interoperability AGP Signal Voltage Tolerance ListConnector Universal Connector Motherboard / Add-in Card Interoperability AGP Left-Handed Retention Mechanism AGP Universal Retention Mechanism RM AMP P/N AGP Left-Handed RM Keep-Out Information Hub Interface Hub Interface Signal Routing Example Bit Hub Interface Strobe Signals Bit Hub Interface Data SignalsBit Hub Interface Buffer Configuration Setting Bit Hub Interface Routing Guidelines MCH ICH2 Hlrefa Hubref Bit Hub Interface Hubref Generation Circuit Specifications Bit Hub Interface Decoupling Guidelines Bit Hub Interface CompensationBit Hub Interface Rcomp Resistor Values Component Hub Interface Trace Rcomp Resistor Value System Bus Ground Plane Reference Additional Host Bus GuidelinesMinimizing Crosstalk on the AGTL+ Interface Additional Considerations IDE InterfaceCable Combination Host-Side/Device-Side Cable Detection Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side IDE Cable Detection Device-Side IDE Cable Detection Device-Side Cable Detection Primary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# Sddreq Secondary IDE Connector RequirementsSiordy IRQ15 SDDACK# ICH2 AC’97- Codec Connection 13. AC’97 Intel 820E Chipset Motherboard CNR Board CNR AC97RESET# Signal DescriptionsCDCDNENAB# Codec Configurations Valid Codec ConfigurationsValid Codec Configurations Invalid Codec Configurations 13.3. AC’97 Routing USB Using Native USB InterfaceMotherboard Implementation ISA Support Recommended USB trace characteristicsDisabling the Native USB Interface of ICH2 SMBus/SMLink Interface 16. I/O Apic Design Recommendation SMBus / SMLink Use Implementation Pull-Up Requirements for SMBus and SMLink Signals RTC PCI External Capacitors RTC Crystal RTC Layout Considerations RTC External Battery Connection Rtcrst External Circuit for ICH2 RTC RTC External Rtcrst Circuit RTC Routing Guidelines Spkr Pin ConsiderationVbias DC Voltage and Noise Measurements RTC-Well Input Strap Requirements ICH2 Pirq Routing Function in ICH2 using the PCI IRQ in IoapicUsage of I/O Apic Interrupt Inputs 16 through LAN Layout Guidelines LAN Connect Component Connection FeaturesPIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd LAN Design Guide Section Reference ICH2 LAN Interconnect GuidelinesLayout Section Previous Design Guide Section Point-to-Point Interconnect Bus TopologiesLOM/CNR Interconnect Configuration Signal Routing and LayoutLength Requirements for Figure Impedances Crosstalk ConsiderationLine Termination General Trace Routing Considerations General LAN Routing Guidelines and Considerations Trace Geometry and Length Power and Ground Connections Ground Plane Separation Layer Board Design Design Guide 111 Intel 82562EH Home/PNA* Guidelines Guidelines for Intel 82562EH Component PlacementCrystals and Oscillators Related Documents Intel 82562EH Component Termination Phoneline Hpna Termination LPF Critical DimensionsEeprom Distance Priority Guideline Distance from LPF to Phone RJ11 Intel 82562ET / Intel 82562EM Component Guidelines Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Terminating Unused Connections Reducing Circuit Inductance LAN Disable Circuit Intel 82562ET/EM Disable Guidelines Lancl Dual-Footprint Analog Interface ICH2 Decoupling Recommendations Power Plane/Pins # Decoupling Capacitor ValueDecoupling Capacitor Recommendation Decoupling Capacitor Layout In-Circuit FWH Flash Bios Programming FWH Flash Bios GuidelinesFWH Flash Bios VPP Design Guidelines Checklist Items Recommendations Reason/Effect ICH2 Design ChecklistPCI Interface Hub Interface FWH Flash Bios InterfaceLAN Interface Eeprom Interface PIRQ#DA Interrupt InterfacePIRQ#H PIRQ#E USB Interface GpioVCCSUS3.3 Processor Signals RTC System ManagementAC’97 Power Miscellaneous SignalsSpkr 5VREF SUS IDE Checklist Checklist Items ISA Bridge ChecklistICH2 AD22 / ISA Bit Hub Interface ICH2 Layout ChecklistIDE Interface USB LAN Connect I/F ICH2 Decoupling Layout Recommendations Yes CK-SKS Clocking 138 Design Guide Term Definition Terminology and Definitions 140 Design Guide Guideline Methodology AGTL+ Design Guidelines Initial Timing Analysis Equation 4. Setup TimeEquation 5. Hold Time Equation 6. Maximum Flight Time IC Parameters Pentium Intel AGTL+ Parameters for Example Calculations1,2 Driver Receiver Clk Example Tfltmax Calculations for 133 MHz Bus1 Pre-Layout Simulation Determine the Desired General Topology, Layout, and RoutingMethodology Sensitivity Analysis Simulation Criteria Monte Carlo Analysis Place and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsLayout and Route Board Trace Width Space Guidelines Host Clock Routing Apic Data Bus RoutingCrosstalk Type Trace WidthSpace Ratio Post-Layout Simulation Intersymbol Interference Crosstalk Analysis ValidationMeasurements Flight Time Simulation Flight Time Hardware Validation Equation 8. Valid Delay EquationSET Q CLR Q AGTL+ TheoryTiming Requirements Aggressor and Victim Networks Crosstalk Theory Potential Termination Crosstalk Problems Textbook Timing Equations More Details and Insight Effective Impedance and Tolerance/Variation Power Distribution Reference Planes and PCB Stack-Up One Signal Layer and One Reference Plane Layer Switch with Multiple Reference Planes Same Type One Layer with Multiple Reference Planes High-Frequency Decoupling Clock Routing Ringback Levels Vref Guard BandOverdrive Region Flight Time Definition and Measurement Conclusion Intel 820E Chipset Platform System Clocks Clock GenerationNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Platform Clock SkewsLPCCLK, Pciclk ±TBD3 Intel 820E Chipset Clock Routing Guidelines1,2 CK133/DRCG Pin Name Component Intel 820E Chipset Platform System Clock Cross-Reference 1 .318 MHz Crystal to CK133 Component Placement and Interconnection Layout Requirements2. CK133 to Drcg MCH to Drcg MCH-to-DRCG Routing Diagram Trace Length DRCG-to-RDRAM ChannelTrace Geometry Clock From Length inches Section Differential Clock Routing Diagram Sections A, C & D External Drcg Component Values1,2 Drcg Impedance Matching CircuitComponent Nominal Value CMID, CMID2 Clock Routing Guidelines for Intel PGA370 Designs AGP Clock Routing GuidelinesSeries Termination Resistors for CK133 Clock Outputs Drcg Layout Example Decoupling Recommendation for CK133 and Drcg Unused OutputsUnused Output Termination Buffer Name CC Range Impedance If Unused Output Drcg Frequency Selection and the DRCG+ Drcg Frequency Selection Table and Jitter Specification DRCG+ Frequency Selection DRCG+ Frequency Selection Schematic PCB Materials Stack-Up Requirement Test Coupon Design Guidelines Design Process Inner-Layer Routing Recommended Stack-UpStack-Up Examples Sample SM max Resin % Field Solver vs. Zcalc Impedance Calculation Tools Board Impedance/Stack-up Summary Testing Board Impedance 182 Design Guide Terminology and Definitions Power DeliveryTerm Definition Intel 820E Chipset Power Delivery Example VCC Dual Switch Vbsy 3VSB V and 2.5 V Power Sequencing Schottky Diode VSB ICH2 1.8 V / 3.3 V Power Sequencing 4 .3V/V5REF Sequencing Example 1.8V/3.3V Power Sequencing Circuit Option 1 Reduce the Clock Frequency During Initialization Excessive Power Consumption by 64/72-Mbit RdramVref Use a GPO to Reduce Drcg Frequency Example of ICH2 Power Plane Split ICH2 Power Plane Split Features Thermal Design PowerIntel 820E Chipset Component Thermal Design Power Component Thermal Design Power 133/400 MHz Vendor Intel Contact Contact Information Glue Chip Vendors Reference Design Feature Set Appendix a Reference Design Schematics Uniprocessor 196 Design Guide Drawn by PCG Platform Design Project PCG AE REVPrairie City Road FOLSOM, California Last Revised Sheet Device Table Block Diagram AH8 AK8AN9 AL9 VCMOS15 CPURST#R2 DBRESET#Gtlref Tckr TDI Tmsr Clock Synthesizer Ramref Hubref RamrefrConnagpref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host GAD0 GAD1 GAD0GAD1 GAD2 GAD2 GAD3 AD1 AD0AD2 AD3 CR4 ACRESET#Vbatcr 1UF Rtcrstjp Fwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 NC1 GndaNC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 RSRV4/RESET SWP SWP RSRV4/RESETTERMDQA80 Rimm LDQA0 Super I/O AC’97 Audio Micin Micinr MicinfbMicinc DB15AUDSTK Communication And Network Riser CNR ACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 Stubs on AC97 LinkRP7 ACSDATAIN0CNR Acsynccnr Acsdataoutcnr LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH H1138ARAGONITE LAN RJ45 For 82562ET/EMLanactled Y5 Xtal Y2 Xtal LANCLKX1 25MHZR381LANCLKX2 LAN Option Intel PART# Stuff for 82562EH Power LED Power SWSW1 VCC12 Irtx TYPEDET# AGP4XU20 AGPOC#USBAGP+ B4 Usbagp Agpclkconn B7 CLK PCI3CON PTRST# Ptck VCC5 VCC12Ptms Ptdi PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Game Port FAULT# IFB VRM Fault VRM IFBVccvid REV Project Imax VRM G1 VRM G2 Voltage Regulators VCC33SBYTG VCC33SBYSW VCC25SBY 1UF-X7RVCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH SBY ITH R Power Connector HREQ#0 BPRI# DBSY# PCI/AGP Pullups/Pulldowns Termcmd Termsck Rambus* Termination Decoupling Bulk Decoupling Drawn by PCG Platform Design Project PCG AE VCMOS18SBY Revision History Drawn by PCG Platform Design Project PCG AE Revision History Probe Connector Hub Interface Connector For debug onlyTESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# HL8 HL4 HL5 HL6 HL7