Intel manual Intel 820E Chipset Clock Routing Guidelines1,2, ±TBD3

Intel® 820E Chipset

R

The following figure shows the Intel 820E chipset clock length routing guidelines.

Figure 87. Intel® 820E Chipset Clock Routing Guidelines1,2

Y

CPUCLK to SC242
	Y	5.3"
CPUCLK to MCH

Note: Tie CPUCLK for the MCH to CPUCLK to the SC242, to eliminate pin-to-pin skew.

±0"

3V66 clock for	Z
AGP slot

PCI clock for

PCI slots

3V66 clock for MCH and ICH

PCI clock for ICH

PCI clock for on-board devices (excluding ICH)

Z 1.5"

Z 4"

Z	4"
Z	4"

±TBD3

±0"

±0"

±TBD3

Note:

1.Tie 3V66 clock for MCH to 3V66 clock for AGP connector, to eliminate pin-to-pin skew.

2.These calculations are based on 150-ps/in trace velocity.

3.TBD value derived from PCI Revision 2.2 Specification, which allows for max. ±2-ns clock skew.

820_clk_route

166 Design Guide