Intel manual Intel 820E Chipset Power Delivery Example

Intel® 820E Chipset

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6.1.2.Power Delivery of Intel® 820E Chipset Customer Reference Board

Figure 101 shows the power delivery architecture for the Intel 820E Chipset Reference Board. This power delivery architecture supports the Instantly Available PC Design Guidelines via the Suspend-to- RAM (STR) state. During STR, only the necessary devices are powered. These devices include main memory, the ICH2 resume well, PCI wake devices (via 3.3 VAUX), and USB. (USB can be powered only if sufficient standby power is available.) To ensure that enough power is available during STR, a thorough power budget must be completed. The power requirements must include each device’s power requirements, both in the suspend and full-power states. The power requirements must be compared with the power budget available from the power supply. Due to the requirements of main memory and PCI 3.3 VAUX—and possibly other devices in the system—it is necessary to create a dual power rail.

Figure 101. Intel® 820E Chipset Power Delivery Example

	ATX P/S			VRM	PGA370 Core: VCC_VID
	with 1A 5VSB
					22A** S0, S1		MBR 2.0 82562EH,
						12V, 3.3V,
5VSB	5V			VTT	PGA370 VTT: 1.5V		82562ET, (PHY) +
		3.3V	12V			3.3VSB, 5V,
				Regulator	2.7A** S0, S1	5VDUAL	Modem Codec S0, S1,
							S3, S5
					CPU CMOS P/Us: 1.5V
5V Dual
Switch				2.5VSBY			DRCG: 3.3V
				Regulator		Diode for	100mA S0, S1
					MCH Core: 1.8V	Sequencing	RDRAM Core: 2.5V
				CK133-2.5:	MCH Hub I/F I/O: 1.8V
					950mA S0, S1	RDRAM VTerm: 1.8V	2.0A S0, S1; 32ma S3
				2.5V	MCH VDDQ: 1.5V/3.3V*
				CK133-3.3:		704mA S0, S1
					2A S0, S1		VCC CMOS: 1.8V
				3.3V
							3mA S0, S1, S3
				1.8V	ICH2
				Regulator	VccCPU-VRM out
					10mA S0, S1
				VDDQ	Vcc1_8-Hub I/F I/O: 1.8V
					300mA S0, S1
				Regulator		VCC2_5 Voltage
					V5Ref: 5V
						Regulator: 2.5V
					<10uA S0, S1
					Vcc3_3: 3.3V
					<300mA S0, S1
					VccSus3_3-ICH Resume:
			3.3VSB		3.3V	PCI 3.3Vaux: 3.3V
					20mA S0, S1; 300uA S3,S5
			Regulator		VccSus1_8-ICH Resume:	1.5A S0, S1; 435ma S3, S5
				1.8VSB	1.8V	LPC Super I/O: 3.3V
				Regulator	210mA S0, S120mA S3, S5
					VccRTC-ICH RTC: Vbat	FWH Flash BIOS
				USB Cable	<4uA S0, S1, S3, S5
					V5RefSus: 5VSB	Core: 3.3V
				Power: 5V		67mA S0, S1
					<10uA S0,S1,S3,S5
				AC'97 Audio
				Codec: 5V

2.5V

1.8V

* Vddq also connects to the AGP connector. 2A is the TOTAL VDDQ current requirement.

**Refer to the Pentium® III processor datasheet for power requirement considerations for PGA370 designs. The Pentium® III processor datasheet can be found at: http://developer.intel.com/design/PentiumIII/datashts/

Shaded regulators/components are on in S3, S5 (Note RDRAM core and VCC CMOS must be OFF in S5)

LEGEND:

ATX Power Planes		Intel® 820E Chipset	Power Planes
	5VSB		5V Dual
	5V		VCCVID
	3.3V		VTT
	12V		2.5VSBY
			1.8V

VDDQ 3.3VSB 2.5V 1.8VSB

Pwr_Delivery

184 Design Guide