Intel 820E Pull-Up Requirements for SMBus and SMLink Signals, SMBus / SMLink Use Implementation

Intel® 820E Chipset

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Figure 57. SMBUS/SMLink Interface

Host controller	SPD data	Network
slave interface
	Temperature on	interface
	thermal sensor	card on PCI
SMBus	SMBCLK	Microcontroller
82801BA
	SMBDATA
ICH2
SMLink	SMLink0
	SMLink1
Wire OR	Intel®
(optional)	8255
		Motherboard
		LAN controller
		smbus_smlink_IF

Note: Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface. Also, Intel does not support access to the ICH2’s SMBus slave interface by the ICH2’s SMBUS host controller.

The following table describes the pull-up requirements for different implementations of the SMBus and SMLink signals.

Table 20. Pull-Up Requirements for SMBus and SMLink Signals

SMBus / SMLink Use	Implementation
Alert-on-LAN* signals	4.7 kΩ pull-up resistors to 3.3 VSB are required.
GPIOs	Pull-up resistors to 3.3 VSB and the signals must be allowed.

To change states on power-up. (For example, during power-up the ICH2 will drive heartbeat messages until the BIOS programs these signals as GPIOs.) The values of the pull-up resistors depend on the loading on the GPIO signal.

Unused 4.7 kΩ pull-up resistors to 3.3 VSB are required.

Design Guide 95