Intel® 820E Chipset

R

Figure 76. Test Load vs. Actual System Load

I/O BufferVTT

 

 

 

 

 

Vcc

 

 

 

 

 

RTEST

 

 

 

 

 

 

 

 

 

 

Driver pad

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

D

SET Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test load

Driver pin

I/O Buffer

 

VTT

Actual system load

 

Vcc

RTT

Driver pad

CLK

 

 

 

 

 

 

 

D SET Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR Q

 

 

 

 

 

 

 

 

 

 

 

 

TFLIGHTSYSTEM

Receiver pin

test_actual_load

The previous figure shows the different configurations for TCO testing and flight time simulation. The flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. TCO timings are specified at the driver pin output. TFLIGHT-SYSTEMusually is reported by a simulation tool as the time from the driver pad starting its transition to the time when the receiver’s input pin sees a valid data input. Since both timing numbers (TCO, TFLIGHT-SYSTEM) include propagation time from the pad to the pin, it is necessary to subtract this time (TREF) from the reported flight time to avoid double counting. TREF is defined as the time required for the driver output pin to reach the measurement voltage, VREF, starting from the beginning of the driver transition at the pad. TREF must be generated using the same test load for TCO. Intel provides this timing value in the AGTL+ I/O buffer models.

In this manner, the following valid delay equation is satisfied:

Equation 8. Valid Delay Equation

Valid delay = TCO + TFLIGHT-SYS – TREF = TCO-MEASURED + TFLIGHT-MEASURED

This valid delay equation yields the total time from when the driver sees a valid clock pulse to the time when the receiver sees a valid data input.

3.2.6.3.Flight Time Hardware Validation

When a measurement is made in the actual system, TCO and flight time do not need TREF correction since these are the actual numbers. These measurements include all of the effects pertaining to the driver-system interface, and the same is true for TCO. Therefore, the sum of the measured TCO and the measured flight time must be equal the valid delay calculated previously.

Design Guide

151

Page 151
Image 151
Intel 820E manual Flight Time Hardware Validation, Equation 8. Valid Delay Equation, Set Q Clr Q