Intel 820E manual Chipset Components, Memory Controller Hub MCH, Controller Hub 2 ICH2

Intel® 820E Chipset

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1.3.1.Chipset Components

The Intel 820E chipset consists of the Intel® 82820 Memory Controller Hub (MCH) and the

Intel® 82801BA I/O Controller Hub (ICH2). Additional functionality can be provided through the use of a PCI-to-ISA bridge.

Memory Controller Hub (MCH)

The MCH provides the interconnect between the Direct RDRAM and the system logic. It integrates the following functions:

•Support for single or dual Intel PGA370 processors with a 100 MHz or 133 MHz system bus

•256 MHz, 300 MHz, 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB of Direct

RDRAM

•4⋅ , 1.5 V AGP interface (3.3 V 1⋅ , 2⋅ , and 1.5 V 1⋅ , 2⋅ devices also supported)

•Downstream hub interface for access to the ICH2

In addition, the MCH provides arbitration, buffering, and coherency management for each of these interfaces. Refer to Chapter 2 Layout/Routing Guidelines for more information regarding these interfaces.

I/O Controller Hub 2 (ICH2)

The ICH2 provides the I/O subsystem with access to the rest of the system. Additionally, it integrates many I/O functions. The ICH2 integrates:

•Upstream hub interface for access to the MCH

•Two-channel Ultra ATA/100 bus master IDE controller

•Two USB controllers (expanded capabilities for 4 ports)

•I/O APIC

•SMBus controller

•FWH interface (FWH Flash BIOS)

•LPC interface

•AC’97 2.1 interface

•PCI 2.2 interface

•Integrated system management controller

•Alert on LAN*

•Integrated LAN controller

The ICH2 also contains the arbitration and buffering necessary to ensure efficient utilization of these interfaces. Refer to Section 2 for more information on these interfaces.

16 Design Guide