Intel 820E manual LAN Connect I/F

						Intel® 820E Chipset
	R
Table 46. LAN Connect I/F
		#	Layout Recommendations	Yes	No	Comments
		1	Stack-up: 5 mils wide, 10 mil spacing
		2	Z0 = 60 Ω ± 15%			Signal integrity requirement
		3	LAN max. trace length, ICH2 to CNR :			To meet timing requirements
			L = 3 inches to 9 inches (0.5 inch to 3 inches on
			card)
		4	Stubs due to R-pak CNR/LOM stuffing option			To minimize inductance
			should not be present.
		5	Max. trace lengths, ICH2 to 82562EH/ET/EM :			To meet timing requirements
			L = 4.5 inches to 8.5 inches
		6	Max. mismatch between length of a clock trace and			To meet timing and signal quality
			length of any data trace is 0.5 inch.			requirements
		7	Maintain constant symmetry and spacing between			To meet timing and signal quality
			the traces within a differential pair.			requirements
		8	Keep the total length of each differential pair less			Issues found with traces longer
			than 4 inches.			than 4 inches: IEEE phy
						conformance failures, excessive
						EMI and/or degraded receive BER
		9	Do not route the transmit differential traces within			To minimize crosstalk
			70 mils of the receive differential traces.
		10	Distance between differential traces and any other			To minimize crosstalk
			signal line is 70 mils.
		11	Keep max. separation between differential pairs at			To meet timing and signal quality
			7 mils.			requirements
		12	Differential trace impedance should be controlled to			To meet timing and signal quality
			~100 Ω.			requirements
		13	For high speed signals, the number of corners and			To meet timing and signal quality
			vias should be minimized. If a 90º bend is required,			requirements
			it is advisable to use two 45º bends.
		14	Traces should be routed away from board edges by			This allows the field around the
			a distance greater than the trace height above the			trace to couple more easily to the
			ground plane.			ground plane, rather than to
						adjacent wires or boards.
		15	Do not route traces and vias under crystals or			This will prevent coupling to or
			oscillators.			from the clock.
		16	Ration of trace width to height above the ground			To control trace EMI radiation
			plane should be between 1:1 and 3:1.
		17	Traces between decoupling and I/O filter capacitors			Long and thin lines are more
			should be as short and wide as practical.			inductive and would reduce the
						intended effect of decoupling
						capacitors.
		18	Vias to decoupling capacitors should have sufficient			To decrease series inductance
			diameter.
		19	Avoid routing high-speed LAN or phone line traces			To minimize crosstalk
			near other high-frequency signals associated with a
			video controller, cache controller, CPU or similar
			devices.

Design Guide 135