Intel 820E 2.16. I/O APIC Design Recommendation , 2.17. SMBus/SMLink Interface

Intel® 820E Chipset
R
94 Design Guide
2.16. I/O APIC Design Recommendation
UP systems not using the integrated I/O APIC should comply with the following recommendations:
• On the ICH2
 Connect PICCLK d irectly to ground.
 Connect PICD0 and PICD1 to ground through a 10 kΩ resistor.
• On the processor
 PICCLK must be connected from the clock generator to the PICCLK pin on the processor.
 Connect PICD0 to 2.5 V through 10 kΩ resistors.
 Connect PICD1 to 2.5 V through 10 kΩ resistors.
2.17. SMBus/SMLink Interface
The SMBus interface on the ICH2 is the same as that on the ICH. It uses two signals (SMBCLK,
SMBDATA) to send and receive data from components residing on the bus. These signals are used
exclusively by the SMBus host controller, which resides inside the ICH2. If the SMBus is used only for
the Rambus SPD EEPROMs (one on each RIMM), both signals should be pulled up to 3.3. V with a
4.7 kΩ resistor.
The ICH2 incorporates a new SMLink interface supporting Alert on LAN (AOL), AOL2*, and slave
functionality. It uses two signals (SMLINK[1:0]). SMLINK[0] corresponds to an SMBus clock signal,
and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the SMB slave
interface.
For AOL functionality, the ICH2 transmits heartbeat and event messages over the interface. When the
Intel 82562EM LAN connect component is used, the ICH2’s integrated LAN controller will claim the
SMLink heartbeat and event messages and will send them out over the network. An external, AOL2-
enabled LAN controller (i.e., Intel 82550) connects to the SMLink signals, to receive heartbeat and event
messages as well as to access the ICH2 SMBus slave interface. The slave interface function allows an
external microcontroller to perform various functions. For example, the slave write interface can reset or
wake a system, generate SMI# or interrupts, and send a message. The slave read interface can read the
system power state, read the watchdog timer status, and read system status bits.
Both the SMBus host controller and the SMBus slave interface obey the SMBus protocol, so the two
interfaces can be externally wire-OR’d together, to allow an external management ASIC (e.g., Intel
82550) to access targets on the SMBus as well as the ICH2 slave interface. This is done by connecting
SMLink[0] to SMBCLK and SMLink[1] to SMBDATA. See Figure 57. Since SMBus and SMLINK are
pulled up to VCCSUS3_3, system designers must be sure to properly isolate any device that may be
powered down while VCCSUS3_3 is still active (e.g., thermal sensors).