Main
Intel 820E Chipset
Intel 820E Chipset
2 Design Guide
Contents
Page
Page
Page
Page
Figures
Page
Tables
Page
Revision History
1. Introduction
1.1. About This Design Guide
1.2. Reference Documents
1.3. System Overview
1.3.1. Chipset Components
Memory Controller Hub (MCH)
I/O Controller Hub 2 (ICH2)
FWH Flash BIOS
ISA Bridge
1.3.2. Bandwidth Summary
1.3.3. System Configuration
Page
1.4. Platform Initiatives
1.4.1. Direct Rambus RAM (RDRAM*)
1.4.2. Streaming SIMD Extensions
1.4.3. AGP 2.0.
1.4.4. Hub Interface
1.4.5. Integrated LAN Controller
1.4.6. Ultra ATA/100 Support
1.4.7. Expanded USB Support
1.4.8. Manageability
TCO Timer
Page
1.4.9. AC97
Intel 820E Chipset
24 Design Guide
Figure 4. (A-C) AC97 Connections
1.4.10. Low-Pin-Count (LPC) Interface
Page
2. Layout/Routing Guidelines
2.1. General Recommendations
2.2. Component Quadrant Layout
Page
2.3. Intel 820E Chipset Component Placement
2.4. Core Chipset Routing Recommendations
Page
2.5. Source-Synchronous Strobing
2.6. Differential Clocking/Strobing
2.7. Direct RDRAM* Interface
2.7.1. Stack-Up
2.7.2. Direct RDRAM* Layout Guidelines
2.7.2.1. RSL Routing
Page
Page
2.7.2.2. RSL Termination
2.7.2.3. Direct RDRAM* Ground Plane Reference
3.3-V Plane 1.8-V Plane
Wrong
MCH
RIMM2
Required
3.3-V Plane
2.7.2.4. Direct RDRAM* Connector Compensation
Page
Page
Page
Page
Page
2.7.2.4.1. Direct RDRAM* Channel Connector Compensation Enhancement Recommendation
Page
2.7.2.5. RSL Signal Layer Alternation
MCH
2.7.2.6. Length Matching Methods
Page
2.7.2.7. Via Compensation
2.7.2.8. Length Matching and Via Compensation Example
Intel 820E Chipset
Design Guide 53
Table 8. Line Matching and Via Compensation Example1,2,3,4,5,6,7,8,9,10
2.7.3. Direct RDRAM* Reference Voltage
2.7.4. High-Speed CMOS Routing
2.7.4.1. SIO Routing
2.7.4.2. Suspend-to-RAM Shunt Transistor
2.7.5. Direct RDRAM* Clock Routing
2.7.6. Direct RDRAM* Design Checklist
Page
Page
2.8. AGP 2.0
2.8.1. AGP Interface Signal Groups
Signal Groups
2.8.2. 1 Timing Domain Routing Guidelines
2.8.3. 2/4 Timing Domain Routing Guidelines
Interfaces < 6 Inches
Interfaces > 6 Inches and < 7.25 Inches
All AGP Interfaces
2.8.4. AGP 2.0 Routing Summary
2.8.5. AGP Clock Routing
2.8.6. General AGP Routing Guidelines
2.8.6.1. Recommendations
Decoupling
Ground Reference
2.8.7. VDDQ Generation and TYPEDET#
Page
2.8.8. VREF Generation for AGP 2.0 (2 and 4)
Intel 820E Chipset
GMCH
Design Guide 69
1.5-V AGP Card
2.8.9. Compensation
2.8.10. AGP Pull-Ups
2.8.10.1. AGP Signal Voltage Tolerance List
2.8.11. Motherboard / Add-in Card Interoperability
2.8.12. AGP Universal Retention Mechanism (RM)
Page
2.9. Hub Interface
2.9.1. 8-Bit Hub Interface Routing Guidelines
2.9.1.1. 8-Bit Hub Interface Data Signals
2.9.1.2. 8-Bit Hub Interface Strobe Signals
2.9.1.3. 8-Bit Hub Interface HUBREF Generation/Distribution
Page
2.9.1.4. 8-Bit Hub Interface Compensation
2.9.1.5. 8-Bit Hub Interface Decoupling Guidelines
2.10. System Bus Design Pentium III Processor for the Intel PGA370 Socket Layout Guidelines
2.10.1. System Bus Ground Plane Reference
GND Plane
2.11. Additional Host Bus Guidelines
Minimizing Crosstalk on the AGTL+ Interface
Additional Considerations
2.12. IDE Interface
Cable
2.12.1. Cable Detection for Ultra ATA/66 and Ultra ATA/100
2.12.2. Combination Host-Side/Device-Side Cable Detection
Page
2.12.3. Device-Side Cable Detection
Intel 820E Chipset
Design Guide 83
2.12.4. Primary IDE Connector Requirements
Figure 48. Connection Requirements for Primary IDE Connector
NOTES:
Intel 820E Chipset
2.12.5. Secondary IDE Connector Requirements
Figure 49. Connection Requirements for Secondary IDE Connector
NOTES:
2.13. AC97
2.13.1. AC97 Audio Codec Detect Circuit and Configuration Options
CNR BoardMotherboard
CNR Connector
Intel 820E Chipset
88 Design Guide
CNR BoardMotherboard
CNR Connector
CNR Connector
CNR BoardMotherboard
Page
2.13.2. Communication and Networking Riser (CNR)
2.13.3. AC97 Routing
2.13.4. Motherboard Implementation
2.14. USB
2.14.1. Using Native USB Interface
2.14.3. Disabling the Native USB Interface of ICH2
2.15. ISA Support
2.16. I/O APIC Design Recommendation
2.17. SMBus/SMLink Interface
Page
2.18. PCI
ICH2
2.19. RTC
2.19.1. RTC Crystal
2.19.2. External Capacitors
2.19.3. RTC Layout Considerations
2.19.4. RTC External Battery Connection
2.19.5. RTC External RTCRST Circuit
2.19.6. RTC Routing Guidelines
2.19.7. VBIAS DC Voltage and Noise Measurements
2.19.8. RTC-Well Input Strap Requirements
2.20. SPKR Pin Consideration
2.21. ICH2 PIRQ Routing
ICH2
2.22. LAN Layout Guidelines
2.22.1. ICH2 LAN Interconnect Guidelines
2.22.1.1. Bus Topologies
2.22.1.2. Point-to-Point Interconnect
2.22.1.3. LOM/CNR Interconnect
ICH2 Res. pack CNR PLC card
B APLC C D
2.22.1.4. Signal Routing and Layout
Page
2.22.2. General LAN Routing Guidelines and Considerations
2.22.2.1. General Trace Routing Considerations
2.22.2.1.1. Trace Geometry and Length
2.22.2.1.2. Signal Isolation
2.22.2.2. Power and Ground Connections
2.22.2.2.1. General Power and Ground Plane Considerations
Page
2.22.2.3. 4-Layer Board Design
Top-Layer Routing
Ground Plane
Power Plane
Bottom Layer Routing
Page
2.22.3. Intel 82562EH Home/PNA* Guidelines
2.22.3.1. Power and Ground Connections
2.22.3.2. Guidelines for Intel 82562EH Component Placement
2.22.3.3. Crystals and Oscillators
2.22.3.4. Phoneline HPNA Termination
Page
2.22.3.5.3. Distance from LPF to Phone RJ11
2.22.4. Intel 82562ET / Intel 82562EM Component Guidelines
2.22.4.1. Guidelines for Intel 82562ET / Intel 82562EM Component Placement
2.22.4.2. Crystals and Oscillators
2.22.4.3. Intel 82562ET / Intel 82562EM Component Termination Resistors
2.22.4.4. Critical Dimensions
2.22.4.4.1. Distance from Magnetics Module to RJ45
2.22.4.4.2. Distance from the Intel 82562ET Component to the Magnetics Module
2.22.4.5. Reducing Circuit Inductance
2.22.4.6. Terminating Unused Connections
2.22.4.6.1. Termination Plane Capacitance
Intel 820E Chipset
2.22.5. Intel 82562ET/EM Disable Guidelines
LAN Disable Circuit
Figure 75. Intel 82562ET/EM Disable Circuit
MMBT3906
2.22.6. Intel 82562ET and Intel 82562EH Components Dual- Footprint Guidelines
Page
2.22.7. ICH2 Decoupling Recommendations
Page
2.23. FWH Flash BIOS Guidelines
2.23.1. In-Circuit FWH Flash BIOS Programming
2.23.2. FWH Flash BIOS VPP Design Guidelines
Intel 820E Chipset
2.24. ICH2 Design Checklist
Table 26. PCI Interface
Checklist Items Recommendations Reason/Effect
Intel 820E Chipset
126 Design Guide
Table 27. Hub Interface
Table 28. LAN Interface
Intel 820E Chipset
Design Guide 127
Table 31. Interrupt Interface
Checklist Items Recommendations Reason/Effect
Intel 820E Chipset
128 Design Guide
Table 32. GPIO
Table 33. USB Interface
Intel 820E Chipset
Design Guide 129
Table 34. Power Management
Table 35. Processor Signals
Page
Intel 820E Chipset
Design Guide 131
Table 39. Miscellaneous Signals
Table 40. Power
Intel 820E Chipset
132 Design Guide
Figure 73. 5VREF Circuitry
Vcc supply (3.3 V) 5 V supply
Page
Intel 820E Chipset
134 Design Guide
2.25. ICH2 Layout Checklist
Table 43. 8-Bit Hub Interface
Table 44. IDE Interface
Table 45. USB
Intel 820E Chipset
Design Guide 135
Table 46. LAN Connect I/F
Intel 820E Chipset
136 Design Guide
# Layout Recommendations Yes No Comments
Table 47. AC97
Intel 820E Chipset
Design Guide 137
Table 49. CK-SKS Clocking
# Layout Recommendations Yes No Comments
Page
3. Advanced System Bus Design
3.1. Terminology and Definitions
Page
3.2. AGTL+ Design Guidelines
Guideline Methodology
3.2.1. Initial Timing Analysis
Page
Intel 820E Chipset
144 Design Guide
The following two tables were derived assuming the following:
CLKSKEW = 0.2 ns
3.2.2. Determine the Desired General Topology, Layout, and Routing
3.2.3. Pre-Layout Simulation
3.2.3.1. Methodology
3.2.3.2. Sensitivity Analysis
3.2.3.3. Monte Carlo Analysis
3.2.3.4. Simulation Criteria
3.2.4. Place and Route Board
3.2.4.1. Estimate Component-to-Component Spacing for AGTL+ Signals
3.2.4.2. Layout and Route Board
3.2.4.3. Host Clock Routing
3.2.4.4. APIC Data Bus Routing
ICH2
Intel
PGA370
3.2.5. Post-Layout Simulation
3.2.5.2. Crosstalk Analysis
3.2.5.3. Monte Carlo Analysis
3.2.6. Validation
3.2.6.1. Measurements
3.2.6.2. Flight Time Simulation
3.2.6.3. Flight Time Hardware Validation
3.3. Theory
3.3.1. AGTL+
3.3.2. Timing Requirements
3.3.3. Crosstalk Theory
3.3.3.1. Potential Termination Crosstalk Problems
3.4. More Details and Insight
3.4.1. Textbook Timing Equations
3.4.2. Effective Impedance and Tolerance/Variation
3.4.3. Power/Reference Planes, PCB Stack-Up, and High-Frequency Decoupling
3.4.3.1. Power Distribution
3.4.3.2. Reference Planes and PCB Stack-Up
Page
3.4.3.3. High-Frequency Decoupling
3.4.4. Clock Routing
3.5. Definitions of Flight Time Measurements/Corrections and Signal Quality
3.5.1. VREF Guard Band
3.5.2. Ringback Levels
3.5.3. Overdrive Region
3.5.4. Flight Time Definition and Measurement
3.6. Conclusion
4. Clocking
4.1. Clock Generation
Intel 820E Chipset
164 Design Guide
Figure 86. Intel 820E Chipset Platform Clock Distribution
Intel 820E Chipset
Design Guide 165
Table 56. Intel 820E Chipset Platform Clock Skews
NOTES:
Intel 820E Chipset
166 Design Guide
The following figure shows the Intel 820E chipset clock length routing guidelines.
Figure 87. Intel 820E Chipset Clock Routing Guidelines1,2
Intel 820E Chipset
Design Guide 167
Table 57. Intel 820E Chipset Platform System Clock Cross-Reference
CK133/DRCG Pin Name Component Pin Name
4.2. Component Placement and Interconnection Layout Requirements
4.2.1. 14.318 MHz Crystal to CK133
4.2.2. CK133 to DRCG
Intel 820E Chipset
4.2.3. MCH to DRCG
PclkM PclkN VddIPD Figure 89. MCH-to-DRCG Routing Diagram
Figure 90. Direct RDRAM* Clock Routing Dimensions
RIMM_0 RIMM_1
4.2.4. DRCG-to-RDRAM Channel
Trace Geometry
4.2.5. Trace Length
Intel 820E Chipset
Design Guide 171
CFM/CFM# signal trace (sections A+B) is 2 mils. (Exact length matching is recommended.)
4.3. DRCG Impedance Matching Circuit
Figure 94. DRCG Impedance Matching Network
Table 59. External DRCG Component Values1,2
Component Nominal Value Notes
4.4. AGP Clock Routing Guidelines
4.5. Clock Routing Guidelines for Intel PGA370 Designs
For the Intel 820E chipset/FC-PGA clock routing guidelines, refer to th e
Guide Addendum for the Intel Pentium III Processor for the PGA370 Socket. These guidelines can be
4.6. Series Termination Resistors for CK133 Clock Outputs
4.7. Unused Outputs
4.8. Decoupling Recommendation for CK133 and DRCG
4.9. DRCG Frequency Selection and the DRCG+
4.9.1. DRCG Frequency Selection Table and Jitter Specification
4.9.2. DRCG+ Frequency Selection Schematic
5. System Manufacturing
5.1. Stack-Up Requirement
H
5.1.1. PCB Materials
ST
5.1.2. Design Process
5.1.3. Test Coupon Design Guidelines
5.1.4. Recommended Stack-Up
5.1.5. Inner-Layer Routing
5.1.6. Impedance Calculation Tools
5.1.7. Testing Board Impedance
5.1.8. Board Impedance/Stack-up Summary
~48-mil core
Not Routable
Page
6. System Design Considerations
6.1. Power Delivery
6.1.1. Terminology and Definitions
Intel 820E Chipset
6.1.2. Power Delivery of Intel 820E Chipset Customer Reference Board
Figure 101. Intel 820E Chipset Power Delivery Example
5 V Dual Switch
VCCVID
VTT
VCC 2.5
2.5 VBSY
1.8 V
V
3.3VSB
1.8 VSB
2.5 V
6.1.3. ICH2 1.8 V / 3.3 V Power Sequencing
6.1.4. 3.3V/V5REF Sequencing
6.1.5. Excessive Power Consumption by 64/72-Mbit RDRAM
6.1.5.1. Option 1: Reduce the Clock Frequency During Initialization
6.1.5.2. Option 2: Increase the Current Capability of the 2.5 V Voltage Regulator
6.2. ICH2 Power Plane Split
6.3. Thermal Design Power
6.4. Glue Chip 3 (Intel 820E Chipset Glue Chip)
Features
Page
Appendix A: Reference Design Schematics (Uniprocessor)
Reference Design Feature Set
Page
REVISION 0.5
FCPGA 2 RIMM ICH2 REFERENCE SCHEMATICS
Note that these schematics are preliminary and are subject to change.
INTEL(R) 820E CHIPSET
Block Diagram
Device Table
VID0
370-PIN SOCKET
SKT1
VID3
GND;F36,A37,AC33,Y37
GND;AM22,AJ23,D22,F24,B24,AM26,AJ27,D26,F28,B28,AM30,D30,AF32,AB32,X32,T32
370-PIN SOCKET
4.7UH
ITP Test Port Option
1%
110
Clock Synthesizer
1 OUT IN Active 133MHz,48MHz PLL inactive
Disabled OUT
Enabled* IN
Sprd Spect JP14
MCH
GTLREFB
RAMREFA
RAMREFB
AGPREF
MCH
MMBT3904LT1
ICH2
ICH 2
U21
ICH2
CR8
VCCPU2
VCCPU1
VCCRTC
FWH
Top Block Lock
R310
R304
0.1UF
RIMM Sockets
VCC2_5SBY;A41,A42,A54,A58,B41,B42,B54,B58
RSV_EXP:
RSV_SPARE:
GND;A1,A3,A5,A7,A9,A11,A13,A15,A17,A29,A21,A23,A25,A27,A19,A31, A33,A39
SIO
KYBD/MSE I/F
Super I/O
CLOCKS
INFRARED I/F
AC97 Audio
44
VREFOUT
VREF
RX3D
AC97 Audio
Microphone Input
CD Analog Input
C24
Line_In Analog Input
Communication And Network Riser (CNR)
R60
EEPROMLAN
R59
R75
ICH2 AC97 AND CNR LINK STUFFING OPTIONS
Stuffing Option for
Stuff for LAN Down
Stuff for CNR
Stuff for CNR Stuff for LAN Down
LAN (82562EH)
27
29
36
40
LAN (82562ET/EM)
LAN (RJ11 For 82562EH)
LAN (RJ45 For 82562ET/EM)
25MHZ
LAN
STUFFING FOR EEPROM (U22)
82562EM A05723-001
82562ET A05441-001
20MHZ
LAN
STUFF FOR 82562EH
STUFF FOR GILAD ONLY
NOTES:
STUFF FOR 82562ET/EM ONLYAND 82562ET/EM
System
14
R253
R358
R246
AGP Connector
0 and 1
PCI Connectors
2 and 3 PCI Connectors
IDE Connectors
L7
USB Connectors
C40
C41
C42
L6
Parallel Port
45
RP1
RP2
RP3
Serial Ports
GND_KBMS_FB
Keyboard/Mouse/Floppy
J1 9
14
PS/2 KybdPS/2 Mse
10
Game Port
VRM
VRM requirements are based on VRM8.4 spec .
C104
Voltage Regulators
C268
+ +
C124
VTT 1.5 VOLTAGE REGULATOR
Voltage Regulators
C425
VCC 3.3 Standby Voltage Regulator
SENSE-
C424
Power Connector
98
13 12
6 5
R347
AGTL Termination
HD#45
HD#8
HD#0
HD#9
PCI/AGP Pullups/Pulldowns
PROCESSOR
PCI
Rambus* Termination
1011
Un-used Gates
Backside No Stuff
Decoupling
Revision History
Hub Interface Connector
For debug only.
