Intel 820E 3.3. Theory

Intel® 820E Chipset
R
152 Design Guide
3.3. Theory
3.3.1. AGTL+
AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave switching,
open-drain bus with external pull-up resistors that provide both the high logic level and termination at
each load. The processor AGTL+ drivers contain a full-cycle active pull-up device to improve system
timings. The AGTL+ specification defines the following:
• Termination voltage (VTT)
• Receiver reference voltage (VREF) as a function of termination voltage (VTT)
• Processor termination resistance (RTT)
• Input low voltage (VIL)
• Input high voltage (VIH)
• NMOS on resistance (RONN)
• PMOS on resistance (RONP)
• Edge rate specifications
• Ringback specifications
• Overshoot/undershoot specifications.
• Settling limit
3.3.2. Timing Requirements
The system timing for AGTL+ depends on many things. The following elements combine to determine
the maximum and minimum frequencies supportable by the AGTL+ bus:
• Timing range for each agent in the system
 Clock to output [TCO] (Note that the system load is likely to differ from the “specification”
load, so the TCO observed in the system might differ from the TCO of the specification.)
 Minimum required setup time to clock [TSU_MIN] for each receiving agent
• Range of flight time between each component, including
 Propagation velocity for the loaded printed circuit board [SEFF]
 Board loading effect on the effective TCO in the system
• Amount of skew and jitter in system clock generation and distribution
• Changes in flight time due to crosstalk, noise, and other effects