DS33Z41 Quad IMUX Ethernet Mapper

9.6.2MAC Registers

The control registers related to the control of the individual MACs are shown in the following tables. The DS33Z41 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Note that the addresses listed are the indirect addresses that must be provided to SU.MACRADH/SU.MACRADL or SU.MACAWH/SU.MACAWL.

Register Name:

SU.MACCR

 

 

 

 

 

 

Register Description:

MAC Control Register

 

 

 

 

 

Register Address:

0000h (indirect)

 

 

 

 

 

 

0000h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

31

30

 

29

 

28

27

26

25

24

 

Name

Reserved

Reserved

Reserved

 

HDB

PS

Reserved

Reserved

Reserved

Default

0

0

 

0

 

0

0

0

0

0

 

0001h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

23

22

 

21

 

20

19

18

17

16

 

Name

DRO

Reserved

OML0

 

F

PM

PAM

Reserved

Reserved

Default

0

0

 

0

 

0

0

0

0

0

 

0002h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

14

 

13

 

12

11

10

09

08

 

Name

Reserved

Reserved

Reserved

 

LCC

Reserved

DRTY

Reserved

ASTP

Default

0

0

 

0

 

0

0

0

0

0

 

0003h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

07

06

 

05

 

04

03

02

01

00

 

Name

BOLMT1

BOLMT0

 

DC

 

Reserved

TE

RE

Reserved

Reserved

 

Default

0

0

 

0

 

0

0

0

0

0

 

Bit 28: Heartbeat Disable (HDB). When set to 1, the heartbeat (SQE) function is disabled. This bit should be set to 1 when operating in MII mode.

Bit 27: Port Select (PS). This bit should be equal to 0 for proper operation.

Bit 23: Disable Receive Own (DRO). When set to 1, the MAC disables the reception of frames while TX_EN is asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared when operating in full-duplex mode. This bit must be set to 1 for half-duplex operation.

Bit 21: Loopback Operating Mode (OMLO). When set to 1, data is looped from the transmit side, back to the receive side, without being transmitted to the PHY.

Bit 20: Full-Duplex Mode Select (F). When set to 1, the MAC transmits and receives data simultaneously. When in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.

Bit 19: Promiscuous Mode (PM). When set to 1, the MAC is in Promiscuous Mode and forwards all frames. Note that the default value is 1.

Bit 18: Pass All Multicast (PAM). When set to 1, the MAC forwards Multicast Frames.

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Maxim DS33Z41 specifications MAC Registers, Su.Maccr