Manuals / Maxim / Computer Equipment / Network Card

Maxim DS33Z41 specifications Package Information, 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001

Models: DS33Z41

1 167

Download 167 pages 14.56 Kb

Page 166

Image 166

DS33Z41 Quad IMUX Ethernet Mapper

13 PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.)

13.1 169-Ball CSBGA, 14mm x 14mm (56-G6035-001)

166 of 167

Page 166

Image 166

Maxim DS33Z41 specifications Package Information, 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001

Contents

General Description Functional DiagramFeatures ApplicationsTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights MAC Interface Test and DiagnosticsSdram Interface Microprocessor InterfaceSpecifications compliance T1 Related Telecommunications SpecificationsQuad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time SlotBlock Diagrams Major Operating ModesPin Functional Description Detailed Pin Descriptions Name PIN Type Function Serial Interface IO PinsPIN Descriptions MII/RMII PortName PIN Type Function Transmit Enable MIITransmit Enable Rmii Transmit Data 0 through 1RMII. Two bits of data TXDMdio ColdetMDC Microprocessor PortMode Control Name PIN Type Function Sdram Controller Queue Status Jtag InterfaceVDD1.8 Connect to 1.8V Power Supply Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VSS Connect to the Common Supply GroundDS33Z41 256-Ball Csbga Pinout C D E F G H J K L M NFunctional Description Clear on Read Processor InterfaceRead-Write/Data Strobe Modes Interrupt and Pin ModesRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clock StructureClock Selection for the Ethernet LAN Interface DTE InputClocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock ModesReset Functions Resets and Low-Power ModesReset Function Location Comments Per-Port Resources Initialization and ConfigurationGlobal Resources Example Device Initialization SequenceDevice Interrupts Drawing Legend Interrupt PinSerial Interface Link Aggregation ImuxImux Interface to T1/E1 Transceivers SequenceMicroprocessor Requirements Imux Command Protocol Commands Sent and Received on the Imux LinksOOF Command and Status for the Imux for Processor Communication Register Name CommentsOut of Frame OOF Monitoring Data TransferConnections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Option ModeOptions for Flow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow controlEthernet Interface Port Ieee 802.3 Ethernet FrameDTE and DCE Mode Registers Related to the Ethernet PortConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Status Registers Ethernet MACMAC Control Registers Address Register DescriptionMII Mode Rmii ModeBert Bert FeaturesPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfaceRepetitive Pattern Synchronization Prbs SynchronizationPattern Monitoring Error InsertionPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Register Address Map Device RegistersBert Global Register Bit Map Register Bit MapsGlobal Register Bit Map NameArbiter Register Bit Map Arbiter Register Bit MapBert Register Bit Map Bert Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRepl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie RspcieEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Indirect Register Bit Map MAC Register Bit Map200h GL.IDRL Global Register DefinitionsGL.IDRH GL.CR1 GL.BLRGL.SRCALS GL.RTCAL04h Global Sdram Reference Clock Activity Latched StatusGL.SIE GL.LIEGL.LIS GL.SISGL.IBIE GL.TRQIEGL.TRQIS GL.IBISGL.CON1 GL.C1QPRGL.IMXCN Available User Commands Value CommentGL.IMXC GL.IMXSS GL.IMXSIEGL.IMXDFEIE GL.IMXSLSGL.IMXDFD GL.IMXDFDELSGL.IMXOOFIE Inverse MUX OOF Interrupt Enable1Eh GL.BISTEN GL.IMXOOFLSGL.BISTPF GL.SDMODE2 GL.SDMODE1GL.SDMODEWS 3Dh GL.SDRFTCGlobal Sdram Refresh Time Control SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0AR.RQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.TQSC180h Bert RegistersBert Control Register Bit 7 This bit must be kept low for proper operation82h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 83hBert Pattern Byte 1 Register Bert Pattern Byte 0 Register84h 85hBert Status Register Transmit Error Insertion Control Register88h 8Ch8Eh Bert Status Register Interrupt EnableBert Status Register Latched 90hRBECR2 Receive Bit Count Byte 2 Register Receive Bit Count Byte 1 Register #199h 9AhSerial Interface Transmit Register Bit Descriptions Serial Interface RegistersSerial Interface Transmit and Common Registers LI.RSTPDTransmit Packet Processor Control Low Register Transmit Hdlc Processor RegistersLI.TPPCL 0C4hLI.TIFGC LI.TEPLCLI.TEPHC Transmit Errored Packet High Control RegisterCleanup routine 0C7hLI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR2 LI.TBCR0LI.TBCR1 LI.TBCR3LI.THPMUU LI.THPMUSLI.TRX86A 4 X.86 RegistersLI.TX86EDE LI.TRX8CLI.TRX86SAPIL LI.CIRLI.RPPCL Receive Serial InterfaceLI.RMPSCL LI.RMPSCH LI.RPPSRReceive Packet Processor Status Register Latched LI.RPPSRL105h LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC2 LI.RBC0LI.RBC1 LI.RBC3LI.RAC2 LI.RAC0LI.RAC1 LI.RAC3LI.RHPMUS LI.RHPMUULI.RX86S LI.RX86LSIE LI.TQLTLI.TQTIE LI.TQHTLI.TQCTLS SU.MACRADL Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADHSU.MACRD3 SU.MACRD1SU.MACRD2 SU.MACWD0SU.MACWD3 SU.MACWD1SU.MACWD2 SU.MACAWLSU.MACAWH SU.MACRWCSU.LPBK SU.GCR151h SU.TFRCTransmit Frame Resend Control Ncfq Tprhbc TprcbSU.TFSL SU.TFSHSU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RQLT SU.RMFSRLSU.RMFSRH SU.RQHTSU.QRIE SU.QCRLS15Eh SU.RFRCReceive Frame Rejection Control Ucfr Cfrr Lerr Crcerr DBR Miier BFRMAC Registers SU.MACCRBit Random Number Generator Bits Used SU.MACAH SU.MACALSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh MAC Reserved Control Register010Ch indirect 010Eh0112h 0110h indirect0111h 0113h0200h indirect SU.RxFrmCtrMAC All Frames Received Counter 0201h0204h indirect SU.RxFrmOkCtrMAC Frames Received OK Counter 0205h0300h indirect SU.TxFrmCtrMAC All Frames Transmitted Counter 0301h0308h indirect SU.TxBytesCtrMAC All Bytes Transmitted Counter 0309h030Ch indirect SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030DhSU.TXFRMUNDR 0338h indirect SU.TxBdFrmCtrMAC All Frames Aborted Counter 0339hFunctional Timing MII and Rmii InterfacesMII Receive Functional Timing Operating Parameters DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Recommended DC Operating ConditionsParameter MIN TYP MAX Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow AIR Flow THETA-JA10Mbps 100Mbps Parameter SymbolMII Interface Transmit MII Interface MIN TYP MAXReceive MII Interface Receive MII Interface TimingRmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface TimingMdio Interface -9. Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser TsyncReceive WAN Interface 11. Receive WAN Interface Rclki Rser Rsync100MHz Sdram Timing 12. Sdram Interface TimingSdclko to SRAS, SCAS, SWE, Sdcs Sdata SRAS, ScasLink #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface TimingJtag Functional Block Diagram Jtag InformationJtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction RegisterInstruction Codes for Ieee 1149.1 Architecture Boundary Scan Register Jtag ID Codes ID Code StructureTest Registers Bypass RegisterJtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001Document Revision History Revision Description