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Maxim DS33Z41 specifications Gl.Imxoofie, Inverse MUX OOF Interrupt Enable, 1Eh

Models: DS33Z41

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DS33Z41 Quad IMUX Ethernet Mapper

Register Name:		GL.IMXOOFIE
Register Description:		Inverse MUX OOF Interrupt Enable
Register Address:		1Eh
Bit #	7	6	5	4	3	2	1	0
Name	TOOFIE4	TOOFIE3	TOOFIE2	TOOFIE1	ROOFIE4	ROOFIE3	ROOFIE2	ROOFIE1
Default	0	0	0	0	0	0	0	0

Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4.

Bit 6: IMUX Transmit OOF Interrupt Enable 3 (TOOFIE3). Setting this bit to 1 enables an interrupt on TOOFLS3.

Bit 5: IMUX Transmit OOF Interrupt Enable 2 (TOOFIE2). Setting this bit to 1 enables an interrupt on TOOFLS2.

Bit 4: IMUX Transmit OOF Interrupt Enable 1 (TOOFIE1). Setting this bit to 1 enables an interrupt on TOOFLS1.

Bit 3: IMUX Receive OOF Interrupt Enable 4 (ROOFIE4). Setting this bit to 1 enables an interrupt on ROOFLS4.

Bit 2: IMUX Receive OOF Interrupt Enable 3 (ROOFIE3). Setting this bit to 1 enables an interrupt on ROOFLS3.

Bit 1: IMUX Receive OOF Interrupt Enable 2 (ROOFIE2). Setting this bit to 1 enables an interrupt on ROOFLS2.

Bit 0: IMUX Receive OOF Interrupt Enable 1 (ROOFIE1). Setting this bit to 1 enables an interrupt on ROOFLS1.

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Image 77

Maxim DS33Z41 specifications Gl.Imxoofie, Inverse MUX OOF Interrupt Enable, 1Eh

Contents

Features Functional DiagramGeneral Description ApplicationsTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights Sdram Interface Test and DiagnosticsMAC Interface Microprocessor InterfaceT1 Related Telecommunications Specifications Specifications complianceQuad T1/E1 SCT to DS33Z41 Time Slot Acronyms and GlossaryMajor Operating Modes Block DiagramsPIN Descriptions Name PIN Type Function Serial Interface IO PinsPin Functional Description Detailed Pin Descriptions MII/RMII PortTransmit Enable Rmii Transmit Enable MIIName PIN Type Function Transmit Data 0 through 1RMII. Two bits of data TXDMDC ColdetMdio Microprocessor PortMode Control Name PIN Type Function Sdram Controller Jtag Interface Queue StatusVDD3.3 Connect to 3.3V Power Supply Name PIN Type Function Power SuppliesVDD1.8 Connect to 1.8V Power Supply VSS Connect to the Common Supply GroundC D E F G H J K L M N DS33Z41 256-Ball Csbga PinoutFunctional Description Read-Write/Data Strobe Modes Processor InterfaceClear on Read Interrupt and Pin ModesClock Selection for the Ethernet LAN Interface Clock StructureRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN DTE InputClocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock ModesReset Function Location Comments Resets and Low-Power ModesReset Functions Global Resources Initialization and ConfigurationPer-Port Resources Example Device Initialization SequenceDevice Interrupts Interrupt Pin Drawing LegendLink Aggregation Imux Serial InterfaceSequence Imux Interface to T1/E1 TransceiversMicroprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Register Name Comments Command and Status for the Imux for Processor CommunicationData Transfer Out of Frame OOF MonitoringConnections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow controlIeee 802.3 Ethernet Frame Ethernet Interface PortRegisters Related to the Ethernet Port DTE and DCE ModeConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Control Registers Ethernet MACMAC Status Registers Address Register DescriptionRmii Mode MII ModePHY MII Management Block and Mdio Interface Bert FeaturesBert Repetitive Pattern Synchronization Receive Data InterfaceReceive Pattern Detection Prbs SynchronizationPattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Global Register Bit Map Register Bit MapsGlobal Register Bit Map NameBert Register Bit Map Arbiter Register Bit MapArbiter Register Bit Map Bert Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRepc Rapc Rspc RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie RspcieEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Register Bit Map MAC Indirect Register Bit Map200h GL.IDRH Global Register DefinitionsGL.IDRL GL.BLR GL.CR104h GL.RTCALGL.SRCALS Global Sdram Reference Clock Activity Latched StatusGL.LIS GL.LIEGL.SIE GL.SISGL.TRQIS GL.TRQIEGL.IBIE GL.IBISGL.C1QPR GL.CON1GL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSIE GL.IMXSSGL.IMXDFD GL.IMXSLSGL.IMXDFEIE GL.IMXDFDELS1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 Global Sdram Refresh Time Control GL.SDRFTC3Dh SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0Arbiter Register Bit Descriptions Arbiter RegistersAR.RQSC1 AR.TQSC1Bert Control Register Bert Registers80h Bit 7 This bit must be kept low for proper operationBert Pattern Configuration High Register Bert Pattern Configuration Low Register82h 83h84h Bert Pattern Byte 0 RegisterBert Pattern Byte 1 Register 85h88h Transmit Error Insertion Control RegisterBert Status Register 8ChBert Status Register Latched Bert Status Register Interrupt Enable8Eh 90hRBECR2 99h Receive Bit Count Byte 1 Register #1Receive Bit Count Byte 2 Register 9AhSerial Interface Transmit and Common Registers Serial Interface RegistersSerial Interface Transmit Register Bit Descriptions LI.RSTPDLI.TPPCL Transmit Hdlc Processor RegistersTransmit Packet Processor Control Low Register 0C4hLI.TEPLC LI.TIFGCCleanup routine Transmit Errored Packet High Control RegisterLI.TEPHC 0C7hLI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR1 LI.TBCR0LI.TBCR2 LI.TBCR3LI.THPMUS LI.THPMUULI.TX86EDE 4 X.86 RegistersLI.TRX86A LI.TRX8CLI.CIR LI.TRX86SAPILLI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RPPSR LI.RMPSCH105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC1 LI.RBC0LI.RBC2 LI.RBC3LI.RAC1 LI.RAC0LI.RAC2 LI.RAC3LI.RX86S LI.RHPMUULI.RHPMUS LI.TQLT LI.RX86LSIELI.TQCTLS LI.TQHTLI.TQTIE Ethernet Interface Register Bit Descriptions Ethernet Interface RegistersSU.MACRADL SU.MACRADHSU.MACRD2 SU.MACRD1SU.MACRD3 SU.MACWD0SU.MACWD2 SU.MACWD1SU.MACWD3 SU.MACAWLSU.MACRWC SU.MACAWHSU.GCR SU.LPBKTransmit Frame Resend Control SU.TFRC151h Ncfq Tprhbc TprcbSU.TFSH SU.TFSLSU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RMFSRH SU.RMFSRLSU.RQLT SU.RQHTSU.QCRLS SU.QRIEReceive Frame Rejection Control SU.RFRC15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFRSU.MACCR MAC RegistersBit Random Number Generator Bits Used SU.MACAL SU.MACAHSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Ch indirect MAC Reserved Control Register010Dh 010Eh0111h 0110h indirect0112h 0113hMAC All Frames Received Counter SU.RxFrmCtr0200h indirect 0201hMAC Frames Received OK Counter SU.RxFrmOkCtr0204h indirect 0205hMAC All Frames Transmitted Counter SU.TxFrmCtr0300h indirect 0301hMAC All Bytes Transmitted Counter SU.TxBytesCtr0308h indirect 0309hMAC Bytes Transmitted OK Counter SU.TxBytesOkCtr030Ch indirect 030DhSU.TXFRMUNDR MAC All Frames Aborted Counter SU.TxBdFrmCtr0338h indirect 0339hMII and Rmii Interfaces Functional TimingMII Receive Functional Timing Parameter Symbol Conditions MIN TYP MAX Units DC Electrical CharacteristicsOperating Parameters Recommended DC Operating ConditionsTheta-JA vs. Airflow Thermal Characteristics -3. Thermal CharacteristicsParameter MIN TYP MAX AIR Flow THETA-JAMII Interface Transmit MII Interface Parameter Symbol10Mbps 100Mbps MIN TYP MAXReceive MII Interface Timing Receive MII InterfaceRmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii InterfaceMDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN InterfaceRclki Rser Rsync Receive WAN Interface 11. Receive WAN InterfaceSdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz SRAS, Scas SdataBIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing DiagramJtag Information Jtag Functional Block DiagramJtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State DiagramInstruction Codes for Ieee 1149.1 Architecture Test Registers Jtag ID Codes ID Code StructureBoundary Scan Register Bypass RegisterJtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package InformationRevision Description Document Revision History