Registers Related to the Ethernet Port | Maxim DS33Z41 specs

DS33Z41 Quad IMUX Ethernet Mapper

•MII error asserted during the reception of the frame.

•Dribbling bits occurred in the frame.

•CRC error occurred.

•Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes received.

•Control frame was received. The mode must be full duplex.

•Unsupported control frame was received.

Note that frames received that are runt frames or frames with collision will automatically be rejected.

Table 8-7. Registers Related to the Ethernet Port

REGISTER		FUNCTION

SU.TFRC	This register determines if the current frame is retransmitted due to various
SU.TFRC	transmit errors
	transmit errors
SU.TFSL and SU.TFSH	These 2 registers provide the real time status of the transmit frame. Only apply
SU.TFSL and SU.TFSH	to the last frame transmitted.
	to the last frame transmitted.

SU.RFSB0 to 3	These registers provide the real time status for the received frame. Only apply
SU.RFSB0 to 3	to the last frame received.
	to the last frame received.
SU.RFRC	This register provides settings	for reception or rejection of	frame based	on
SU.RFRC	errors detected by the MAC.
	errors detected by the MAC.
SU.RMFSRH and SU.RMFSRL	The settings for this register	provide the maximum size	of frames to	be
SU.RMFSRH and SU.RMFSRL	accepted from the MII/RMII receive interface.
	accepted from the MII/RMII receive interface.

SU.MACCR	This register provides configuration control for the MAC

8.13.1 DTE and DCE Mode

The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE connections for the DS33Z41 in MII mode are shown in the following two figures.

In DCE Mode, the DS33Z41 transmitter is connected to an external receiver and DS33Z41 receiver is connected to an external MAC transmitter. The selection of DTE or DCE mode is done by the hardware pin DCEDTES.

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Maxim DS33Z41 specifications Registers Related to the Ethernet Port, DTE and DCE Mode

Contents

Applications Functional DiagramFeatures General Description Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights Microprocessor Interface Test and DiagnosticsSdram Interface MAC Interface T1 Related Telecommunications Specifications Specifications compliance Quad T1/E1 SCT to DS33Z41 Time Slot Acronyms and Glossary Major Operating Modes Block Diagrams MII/RMII Port Name PIN Type Function Serial Interface IO PinsPIN Descriptions Pin Functional Description Detailed Pin Descriptions Transmit Data 0 through 1RMII. Two bits of data TXD Transmit Enable MIITransmit Enable Rmii Name PIN Type Function Microprocessor Port ColdetMDC Mdio Mode Control Name PIN Type Function Sdram Controller Jtag Interface Queue Status VSS Connect to the Common Supply Ground Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VDD1.8 Connect to 1.8V Power Supply C D E F G H J K L M N DS33Z41 256-Ball Csbga Pinout Functional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on Read DTE Input Clock StructureClock Selection for the Ethernet LAN Interface Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock Modes Reset Functions Resets and Low-Power ModesReset Function Location Comments Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port Resources Device Interrupts Interrupt Pin Drawing Legend Link Aggregation Imux Serial Interface Sequence Imux Interface to T1/E1 Transceivers Microprocessor Requirements Imux Command Protocol Commands Sent and Received on the Imux LinksOOF Register Name Comments Command and Status for the Imux for Processor Communication Data Transfer Out of Frame OOF Monitoring Connections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Option ModeOptions for Flow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow control Ieee 802.3 Ethernet Frame Ethernet Interface Port Registers Related to the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Address Register Description Ethernet MACMAC Control Registers MAC Status Registers Rmii Mode MII Mode Bert Bert FeaturesPHY MII Management Block and Mdio Interface Prbs Synchronization Receive Data InterfaceRepetitive Pattern Synchronization Receive Pattern Detection Pattern Monitoring Error InsertionPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Register Address Map Device RegistersBert Name Register Bit MapsGlobal Register Bit Map Global Register Bit Map Bert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h GL.IDRL Global Register DefinitionsGL.IDRH GL.BLR GL.CR1 Global Sdram Reference Clock Activity Latched Status GL.RTCAL04h GL.SRCALS GL.SIS GL.LIEGL.LIS GL.SIE GL.IBIS GL.TRQIEGL.TRQIS GL.IBIE GL.C1QPR GL.CON1 GL.IMXCN Available User Commands Value CommentGL.IMXC GL.IMXSIE GL.IMXSS GL.IMXDFDELS GL.IMXSLSGL.IMXDFD GL.IMXDFEIE GL.IMXOOFIE Inverse MUX OOF Interrupt Enable1Eh GL.BISTEN GL.IMXOOFLSGL.BISTPF GL.SDMODE2 GL.SDMODE1GL.SDMODEWS SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 GL.SDRFTCGlobal Sdram Refresh Time Control 3Dh AR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC1 Bit 7 This bit must be kept low for proper operation Bert RegistersBert Control Register 80h 83h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 82h 85h Bert Pattern Byte 0 Register84h Bert Pattern Byte 1 Register 8Ch Transmit Error Insertion Control Register88h Bert Status Register 90h Bert Status Register Interrupt EnableBert Status Register Latched 8Eh RBECR2 9Ah Receive Bit Count Byte 1 Register #199h Receive Bit Count Byte 2 Register LI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers Serial Interface Transmit Register Bit Descriptions 0C4h Transmit Hdlc Processor RegistersLI.TPPCL Transmit Packet Processor Control Low Register LI.TEPLC LI.TIFGC 0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHC LI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2 LI.THPMUS LI.THPMUU LI.TRX8C 4 X.86 RegistersLI.TX86EDE LI.TRX86A LI.CIR LI.TRX86SAPIL LI.RPPCL Receive Serial InterfaceLI.RMPSCL LI.RPPSR LI.RMPSCH Receive Packet Processor Status Register Latched LI.RPPSRL105h LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2 LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2 LI.RHPMUS LI.RHPMUULI.RX86S LI.TQLT LI.RX86LSIE LI.TQTIE LI.TQHTLI.TQCTLS SU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADL SU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3 SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3 SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Ncfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151h SU.TFSH SU.TFSL SU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLT SU.QCRLS SU.QRIE Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15Eh SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACAL SU.MACAH SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Eh MAC Reserved Control Register010Ch indirect 010Dh 0113h 0110h indirect0111h 0112h 0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect 0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect 0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect 0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect 030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirect SU.TXFRMUNDR 0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirect MII and Rmii Interfaces Functional Timing MII Receive Functional Timing Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Operating Parameters AIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAX MIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100Mbps Receive MII Interface Timing Receive MII Interface Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface Mdio Interface -9. Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rser Rsync Receive WAN Interface 11. Receive WAN Interface 100MHz Sdram Timing 12. Sdram Interface TimingSdclko to SRAS, SCAS, SWE, Sdcs SRAS, Scas Sdata BIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing Diagram Jtag Information Jtag Functional Block Diagram Jtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State Diagram Instruction Codes for Ieee 1149.1 Architecture Bypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan Register Jtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package Information Revision Description Document Revision History