
DS33Z41 Quad IMUX Ethernet Mapper
Register Name: | SU.TXFRMUNDR |
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Register Description: | MAC Transmit Frame Under Run Counter |
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Register Address: | 0334h (indirect) |
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0334h: |
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Bit # | 31 | 30 | 29 |
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| 28 | 27 | 26 | 25 | 24 |
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Name | TXFRMU31 | TXFRMU30 | TXFRMU29 |
| TXFRMU28 | TXFRMU27 | TXFRMU26 | TXFRMU25 | TXFRMU24 | ||
Default | 0 | 0 | 0 |
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| 0 | 0 | 0 | 0 | 0 |
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0335h: |
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Bit # | 23 | 22 | 21 |
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| 20 | 19 | 18 | 17 | 16 |
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Name | TXFRMU23 | TXFRMU22 | TXFRMU21 |
| TXFRMU20 | TXFRMU19 | TXFRMU18 | TXFRMU17 | TXFRMU16 | ||
Default | 0 | 0 | 0 |
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| 0 | 0 | 0 | 0 | 0 |
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0336h: |
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Bit # | 15 | 14 | 13 |
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| 12 | 11 | 10 | 09 | 08 |
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Name | TXFRMU15 | TXFRMU14 | TXFRMU13 |
| TXFRMU12 | TXFRMU11 | TXFRMU10 | TXFRMU9 | TXFRMU8 | ||
Default | 0 | 0 | 0 |
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| 0 | 0 | 0 | 0 | 0 |
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0337h: |
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Bit # | 07 | 06 | 05 |
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| 04 | 03 | 02 | 01 | 00 |
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Name | TXFRMU7 | TXFRMU6 | TXFRMU5 |
| TXFRMU4 | TXFRMU3 | TXFRMU2 | TXFRMU1 | TXFRMU0 |
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Default | 0 | 0 | 0 |
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| 0 | 0 | 0 | 0 | 0 |
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Bits 31 to 0: Frames Aborted Due to FIFO Under Run Counter (TXFRMU31 to TXFRMU0).
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