Feature Highlights | Maxim DS33Z41 specs

DS33Z41 Quad IMUX Ethernet Mapper

2 FEATURE HIGHLIGHTS

2.1General

•169-pin, 14mm x 14mm CSBGA package

•1.8V supply with 3.3V tolerant inputs and outputs

•IEEE 1149.1 JTAG boundary scan

•Software access to device ID and silicon revision

•Development support includes evaluation kit, driver source code, and reference designs

2.2Link Aggregation (Inverse Multiplexing)

•Link aggregation for up to 4 T1/E1 Links

•8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers

•Differential delay compensation up to 7.75ms for the 4 T1/E1 links

•Handshaking protocol between local and distant end for establishment of aggregation

2.3HDLC

•HDLC controller engine

•Compatible with polled or interrupt driven environments

•Programmable FCS insertion and extraction

•Programmable FCS type

•Supports FCS error insertion

•Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)

•Supports bit stuffing/destuffing

•Selectable packet scrambling/descrambling (X43+1)

•Separate FCS errored packet and aborted packet counts

•Programmable inter-frame fill for transmit HDLC

2.4Committed Information Rate (CIR) Controller

•CIR controller limits transmission of data from the Ethernet Interface to the Serial Interface.

•CIR granularity at 512kbps

•CIR Averaging for smoothing traffic peaks

2.5X.86 Support

•Programmable X.86 address/control fields for transmit and receive

•Programmable 2-byte protocol (SAPI) field for transmit and receive

•32 bit FCS

•Transmit Transparency processing - 7E is replaced by 7D, 5E

•Transmit Transparency processing – 7D replaced by 7D, 5D

•Receive rate adaptation (7D, DD) is deleted.

•Receive Transparency processing - 7D, 5E is replaced by 7E

•Receive Transparency processing – 7D, 5D is replaced by 7D

•Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect

•Self-synchronizing X43+1 payload scrambling.

•Frame indication due to bad Address/Control/SAPI, FCS error, abort sequence or frame size longer than preset max.

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Maxim DS33Z41 specifications Feature Highlights

Contents

Functional Diagram FeaturesGeneral Description Applications Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights Test and Diagnostics Sdram InterfaceMAC Interface Microprocessor Interface Specifications compliance T1 Related Telecommunications Specifications Quad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time Slot Block Diagrams Major Operating Modes Name PIN Type Function Serial Interface IO Pins PIN DescriptionsPin Functional Description Detailed Pin Descriptions MII/RMII Port Transmit Enable MII Transmit Enable RmiiName PIN Type Function Transmit Data 0 through 1RMII. Two bits of data TXD Coldet MDCMdio Microprocessor Port Mode Control Name PIN Type Function Sdram Controller Queue Status Jtag Interface Name PIN Type Function Power Supplies VDD3.3 Connect to 3.3V Power SupplyVDD1.8 Connect to 1.8V Power Supply VSS Connect to the Common Supply Ground DS33Z41 256-Ball Csbga Pinout C D E F G H J K L M N Functional Description Processor Interface Read-Write/Data Strobe ModesClear on Read Interrupt and Pin Modes Clock Structure Clock Selection for the Ethernet LAN InterfaceRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN DTE Input Clocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Function Location Comments Resets and Low-Power ModesReset Functions Initialization and Configuration Global ResourcesPer-Port Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Interrupt Pin Serial Interface Link Aggregation Imux Imux Interface to T1/E1 Transceivers Sequence Microprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Command and Status for the Imux for Processor Communication Register Name Comments Out of Frame OOF Monitoring Data Transfer Connections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow control Ethernet Interface Port Ieee 802.3 Ethernet Frame DTE and DCE Mode Registers Related to the Ethernet Port Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Ethernet MAC MAC Control RegistersMAC Status Registers Address Register Description MII Mode Rmii Mode PHY MII Management Block and Mdio Interface Bert FeaturesBert Receive Data Interface Repetitive Pattern SynchronizationReceive Pattern Detection Prbs Synchronization Pattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Register Bit Maps Global Register Bit MapGlobal Register Bit Map Name Arbiter Register Bit Map Bert Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8 Repc Rapc RspcRepl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h GL.IDRH Global Register DefinitionsGL.IDRL GL.CR1 GL.BLR GL.RTCAL 04hGL.SRCALS Global Sdram Reference Clock Activity Latched Status GL.LIE GL.LISGL.SIE GL.SIS GL.TRQIE GL.TRQISGL.IBIE GL.IBIS GL.CON1 GL.C1QPR GL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSS GL.IMXSIE GL.IMXSLS GL.IMXDFDGL.IMXDFEIE GL.IMXDFDELS 1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 GL.SDRFTC Global Sdram Refresh Time Control3Dh SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 Arbiter Registers Arbiter Register Bit DescriptionsAR.RQSC1 AR.TQSC1 Bert Registers Bert Control Register80h Bit 7 This bit must be kept low for proper operation Bert Pattern Configuration Low Register Bert Pattern Configuration High Register82h 83h Bert Pattern Byte 0 Register 84hBert Pattern Byte 1 Register 85h Transmit Error Insertion Control Register 88hBert Status Register 8Ch Bert Status Register Interrupt Enable Bert Status Register Latched8Eh 90h RBECR2 Receive Bit Count Byte 1 Register #1 99hReceive Bit Count Byte 2 Register 9Ah Serial Interface Registers Serial Interface Transmit and Common RegistersSerial Interface Transmit Register Bit Descriptions LI.RSTPD Transmit Hdlc Processor Registers LI.TPPCLTransmit Packet Processor Control Low Register 0C4h LI.TIFGC LI.TEPLC Transmit Errored Packet High Control Register Cleanup routineLI.TEPHC 0C7h LI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR0 LI.TBCR1LI.TBCR2 LI.TBCR3 LI.THPMUU LI.THPMUS 4 X.86 Registers LI.TX86EDELI.TRX86A LI.TRX8C LI.TRX86SAPIL LI.CIR LI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RPPSR 105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC0 LI.RBC1LI.RBC2 LI.RBC3 LI.RAC0 LI.RAC1LI.RAC2 LI.RAC3 LI.RX86S LI.RHPMUULI.RHPMUS LI.RX86LSIE LI.TQLT LI.TQCTLS LI.TQHTLI.TQTIE Ethernet Interface Registers Ethernet Interface Register Bit DescriptionsSU.MACRADL SU.MACRADH SU.MACRD1 SU.MACRD2SU.MACRD3 SU.MACWD0 SU.MACWD1 SU.MACWD2SU.MACWD3 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR SU.TFRC Transmit Frame Resend Control151h Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RMFSRL SU.RMFSRHSU.RQLT SU.RQHT SU.QRIE SU.QCRLS SU.RFRC Receive Frame Rejection Control15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACAH SU.MACAL SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL MAC Reserved Control Register 010Ch indirect010Dh 010Eh 0110h indirect 0111h0112h 0113h SU.RxFrmCtr MAC All Frames Received Counter0200h indirect 0201h SU.RxFrmOkCtr MAC Frames Received OK Counter0204h indirect 0205h SU.TxFrmCtr MAC All Frames Transmitted Counter0300h indirect 0301h SU.TxBytesCtr MAC All Bytes Transmitted Counter0308h indirect 0309h SU.TxBytesOkCtr MAC Bytes Transmitted OK Counter030Ch indirect 030Dh SU.TXFRMUNDR SU.TxBdFrmCtr MAC All Frames Aborted Counter0338h indirect 0339h Functional Timing MII and Rmii Interfaces MII Receive Functional Timing DC Electrical Characteristics Parameter Symbol Conditions MIN TYP MAX UnitsOperating Parameters Recommended DC Operating Conditions Thermal Characteristics -3. Thermal Characteristics Theta-JA vs. AirflowParameter MIN TYP MAX AIR Flow THETA-JA Parameter Symbol MII Interface Transmit MII Interface10Mbps 100Mbps MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface Timing MDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser Tsync Receive WAN Interface 11. Receive WAN Interface Rclki Rser Rsync Sdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz Sdata SRAS, Scas Link #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface Timing Jtag Functional Block Diagram Jtag Information Jtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Jtag ID Codes ID Code Structure Test RegistersBoundary Scan Register Bypass Register Jtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Document Revision History Revision Description