Maxim DS33Z41 Jtag ID Codes ID Code Structure, Test Registers, Boundary Scan Register

DS33Z41 Quad IMUX Ethernet Mapper

12.3 JTAG ID Codes

Table 12-2. ID Code Structure

DEVICE	REVISION	DEVICE CODE	MANUFACTURER’S CODE	REQUIRED
	ID[31:28]	ID[27:12]	ID[11:1]	ID[0]
DS33Z41	0000	0000 0000 0110 0010	000 1010 0001	1

12.4 Test Registers

IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the device design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.

12.4.1 Boundary Scan Register

This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length.

12.4.2 Bypass Register

This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO.

12.4.3 Identification Register

The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.

164 of 167