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Maxim DS33Z41 specifications Configured as DTE Connected to an Ethernet PHY in MII Mode

Models: DS33Z41

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DS33Z41 Quad IMUX Ethernet Mapper

Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode

	DS33Z41
	Rx		Ethernet Phy
		RXD[3:0]	RXD[3:0]	Rx
	DTE	RXDV	RXDV	DCE
		RXDV	RXDV
		RX_CLK	RX_CLK
		RX_ERR	RX_ERR
Arbiter		RX_CRS	RX_CRS
WAN	MAC COL_DET		COL_DET
		TXD[3:0]	TXD[3:0]
			TX_CLK	Tx
	Tx	TX_CLK	TX_CLK
		TX_EN	TX_EN
		TX_EN
		MDIO	MDIO
			MDIO
		MDC	MDC

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Image 44

Maxim DS33Z41 specifications Configured as DTE Connected to an Ethernet PHY in MII Mode

Contents

Functional Diagram FeaturesGeneral Description ApplicationsTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights Test and Diagnostics Sdram InterfaceMAC Interface Microprocessor InterfaceSpecifications compliance T1 Related Telecommunications SpecificationsQuad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time SlotBlock Diagrams Major Operating ModesName PIN Type Function Serial Interface IO Pins PIN DescriptionsPin Functional Description Detailed Pin Descriptions MII/RMII PortTransmit Enable MII Transmit Enable RmiiName PIN Type Function Transmit Data 0 through 1RMII. Two bits of data TXDColdet MDCMdio Microprocessor PortMode Control Name PIN Type Function Sdram Controller Queue Status Jtag InterfaceName PIN Type Function Power Supplies VDD3.3 Connect to 3.3V Power SupplyVDD1.8 Connect to 1.8V Power Supply VSS Connect to the Common Supply GroundDS33Z41 256-Ball Csbga Pinout C D E F G H J K L M NFunctional Description Processor Interface Read-Write/Data Strobe ModesClear on Read Interrupt and Pin ModesClock Structure Clock Selection for the Ethernet LAN InterfaceRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN DTE InputClocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock ModesReset Function Location Comments Resets and Low-Power ModesReset Functions Initialization and Configuration Global ResourcesPer-Port Resources Example Device Initialization SequenceDevice Interrupts Drawing Legend Interrupt PinSerial Interface Link Aggregation ImuxImux Interface to T1/E1 Transceivers SequenceMicroprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Command and Status for the Imux for Processor Communication Register Name CommentsOut of Frame OOF Monitoring Data TransferConnections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow controlEthernet Interface Port Ieee 802.3 Ethernet FrameDTE and DCE Mode Registers Related to the Ethernet PortConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Ethernet MAC MAC Control RegistersMAC Status Registers Address Register DescriptionMII Mode Rmii ModePHY MII Management Block and Mdio Interface Bert FeaturesBert Receive Data Interface Repetitive Pattern SynchronizationReceive Pattern Detection Prbs SynchronizationPattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Register Bit Maps Global Register Bit MapGlobal Register Bit Map NameArbiter Register Bit Map Bert Register Bit MapArbiter Register Bit Map Bert Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8 Repc Rapc RspcRepl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie RspcieEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Indirect Register Bit Map MAC Register Bit Map200h GL.IDRH Global Register DefinitionsGL.IDRL GL.CR1 GL.BLRGL.RTCAL 04hGL.SRCALS Global Sdram Reference Clock Activity Latched StatusGL.LIE GL.LISGL.SIE GL.SISGL.TRQIE GL.TRQISGL.IBIE GL.IBISGL.CON1 GL.C1QPRGL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSS GL.IMXSIEGL.IMXSLS GL.IMXDFDGL.IMXDFEIE GL.IMXDFDELS1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 GL.SDRFTC Global Sdram Refresh Time Control3Dh SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0Arbiter Registers Arbiter Register Bit DescriptionsAR.RQSC1 AR.TQSC1Bert Registers Bert Control Register80h Bit 7 This bit must be kept low for proper operationBert Pattern Configuration Low Register Bert Pattern Configuration High Register82h 83hBert Pattern Byte 0 Register 84hBert Pattern Byte 1 Register 85hTransmit Error Insertion Control Register 88hBert Status Register 8ChBert Status Register Interrupt Enable Bert Status Register Latched8Eh 90hRBECR2 Receive Bit Count Byte 1 Register #1 99hReceive Bit Count Byte 2 Register 9AhSerial Interface Registers Serial Interface Transmit and Common RegistersSerial Interface Transmit Register Bit Descriptions LI.RSTPDTransmit Hdlc Processor Registers LI.TPPCLTransmit Packet Processor Control Low Register 0C4hLI.TIFGC LI.TEPLCTransmit Errored Packet High Control Register Cleanup routineLI.TEPHC 0C7hLI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR0 LI.TBCR1LI.TBCR2 LI.TBCR3LI.THPMUU LI.THPMUS4 X.86 Registers LI.TX86EDELI.TRX86A LI.TRX8CLI.TRX86SAPIL LI.CIRLI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RPPSR105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC0 LI.RBC1LI.RBC2 LI.RBC3LI.RAC0 LI.RAC1LI.RAC2 LI.RAC3LI.RX86S LI.RHPMUULI.RHPMUS LI.RX86LSIE LI.TQLTLI.TQCTLS LI.TQHTLI.TQTIE Ethernet Interface Registers Ethernet Interface Register Bit DescriptionsSU.MACRADL SU.MACRADHSU.MACRD1 SU.MACRD2SU.MACRD3 SU.MACWD0SU.MACWD1 SU.MACWD2SU.MACWD3 SU.MACAWLSU.MACAWH SU.MACRWCSU.LPBK SU.GCRSU.TFRC Transmit Frame Resend Control151h Ncfq Tprhbc TprcbSU.TFSL SU.TFSHSU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RMFSRL SU.RMFSRHSU.RQLT SU.RQHTSU.QRIE SU.QCRLSSU.RFRC Receive Frame Rejection Control15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFRMAC Registers SU.MACCRBit Random Number Generator Bits Used SU.MACAH SU.MACALSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL MAC Reserved Control Register 010Ch indirect010Dh 010Eh0110h indirect 0111h0112h 0113hSU.RxFrmCtr MAC All Frames Received Counter0200h indirect 0201hSU.RxFrmOkCtr MAC Frames Received OK Counter0204h indirect 0205hSU.TxFrmCtr MAC All Frames Transmitted Counter0300h indirect 0301hSU.TxBytesCtr MAC All Bytes Transmitted Counter0308h indirect 0309hSU.TxBytesOkCtr MAC Bytes Transmitted OK Counter030Ch indirect 030DhSU.TXFRMUNDR SU.TxBdFrmCtr MAC All Frames Aborted Counter0338h indirect 0339hFunctional Timing MII and Rmii InterfacesMII Receive Functional Timing DC Electrical Characteristics Parameter Symbol Conditions MIN TYP MAX UnitsOperating Parameters Recommended DC Operating ConditionsThermal Characteristics -3. Thermal Characteristics Theta-JA vs. AirflowParameter MIN TYP MAX AIR Flow THETA-JAParameter Symbol MII Interface Transmit MII Interface10Mbps 100Mbps MIN TYP MAXReceive MII Interface Receive MII Interface TimingRmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface TimingMDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser TsyncReceive WAN Interface 11. Receive WAN Interface Rclki Rser RsyncSdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz Sdata SRAS, ScasLink #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface TimingJtag Functional Block Diagram Jtag InformationJtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction RegisterInstruction Codes for Ieee 1149.1 Architecture Jtag ID Codes ID Code Structure Test RegistersBoundary Scan Register Bypass RegisterJtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001Document Revision History Revision Description