DS33Z41 Quad IMUX Ethernet Mapper

Register Name:

SU.TxBytesCtr

 

 

 

 

 

 

Register Description:

MAC All Bytes Transmitted Counter

 

 

 

 

Register Address:

0308h (indirect)

 

 

 

 

 

0308h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

31

30

29

 

 

28

27

26

25

24

 

Name

TXBYTEC31

TXBYTEC30

TXBYTEC29

 

TXBYTEC28

TXBYTEC27

TXBYTEC26

TXBYTEC25

TXBYTEC24

Default

0

0

0

 

 

0

0

0

0

0

 

0309h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

23

22

21

 

 

20

19

18

17

16

 

Name

TXBYTEC23

TXBYTEC22

TXBYTEC21

 

TXBYTEC20

TXBYTEC19

TXBYTEC18

TXBYTEC17

TXBYTEC16

Default

0

0

0

 

 

0

0

0

0

0

 

030Ah:

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

14

13

 

 

12

11

10

09

08

 

Name

TXBYTEC15

TXBYTEC14

TXBYTEC13

 

TXBYTEC12

TXBYTEC11

TXBYTEC10

TXBYTEC9

TXBYTEC8

Default

0

0

0

 

 

0

0

0

0

0

 

030Bh:

 

 

 

 

 

 

 

 

 

 

 

Bit #

07

06

05

 

 

04

03

02

01

00

 

Name

TXBYTEC7

TXBYTEC6

TXBYTEC5

 

TXBYTEC4

TXBYTEC3

TXBYTEC2

TXBYTEC1

TXBYTEC0

 

Default

0

0

0

 

 

0

0

0

0

0

 

Bits 31 to 0: All Bytes Transmitted Counter (TXBYTEC31 to TXBYTEC0). 32-bit value indicating the number of bytes transmitted. Each time a byte is transmitted, this counter is incremented by 1. This counter resets only upon device reset, does not saturate, and rolls over to zero upon reaching the maximum value. The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum data rate. The user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover occurring.

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Image 136
Maxim DS33Z41 specifications SU.TxBytesCtr, MAC All Bytes Transmitted Counter, 0308h indirect, 0309h, 030Ah, 030Bh