
DS33Z41 Quad IMUX Ethernet Mapper
Register Name: |
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| GL.LIE |
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Register Description: |
| Global Serial Interface Interrupt Enable |
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Register Address: |
| 06h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |||
Name |
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| — | — |
| — | LIN1TIE | — |
| — | — | LIN1RIE |
Default |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bit 4: Serial Interface 1 Tx Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS.
Bit 0: Serial Interface 1 Rx Interrupt Enable (LINE1RIE). Setting this bit to 1 enables an interrupt on LIN1RIS.
Register Name: |
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| GL.LIS |
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Register Description: |
| Global Serial Interface Interrupt Status |
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Register Address: |
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| 07h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |||
Name |
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| - | - |
| - | LIN1TIS | - |
| - | - | LIN1RIS |
Default |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bit 4: Serial Interface 1 Tx Interrupt Status (LIN1TIS). This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Bit 0: Serial Interface 1 Rx Interrupt Status (LIN1RIS). This bit is set if Serial Interface 1 Receive has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Register Name: |
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| GL.SIE |
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Register Description: |
| Global Ethernet Interface Interrupt Enable |
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Register Address: |
| 08h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |||
Name |
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| — | — |
| — | — | — |
| — | — | SUB1IE |
Default |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bit 0: Ethernet Interface 1 Interrupt Enable (SUB1IE). Setting this bit to 1 enables an interrupt on SUB1S.
Register Name: |
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| GL.SIS |
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Register Description: |
| Global Ethernet Interface Interrupt Status |
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Register Address: |
| 09h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |||
Name |
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| — | — |
| — | — | — |
| — | — | SUB1IS |
Default |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bit 0: Ethernet Interface 1 Interrupt Status (SUB1IS). This bit is set to 1 if Ethernet Interface 1 has an enabled interrupt generating event. The Ethernet Interface consists of the MAC and The RMII/MII port.
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