DS33Z41 Quad IMUX Ethernet Mapper
Register Name: |
| TEICR |
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Register Description: |
| Transmit Error Insertion Control Register |
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Register Address: |
| 88h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |
Name | — | — |
| TIER2 | TIER1 | TIER0 |
| BEI | TSEI | — |
Default | 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bits 5 to 3: Transmit Error Insertion Rate (TEIR2 to TEIR0). These three bits indicate the rate at which errors are inserted in the output data stream. One out of every 10n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A TEIR[2:0] value of 2 results in every 100th bit being inverted. Error insertion starts when this register is written to with a TEIR[2:0] value that is
Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If this bit transitions more than once between error insertion opportunities, only one error is inserted.
All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation.
Register Name: |
| BSR |
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Register Description: |
| BERT Status Register |
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Register Address: |
| 8Ch |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Name | — | — |
| — | — | PMS | — | BEC | OOS |
Default | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 |
Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is asynchronously forced low when the PMU bit goes low. TCLKI and RCLKI must be present.
Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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