Link #1, Channel #1 Rsync Rser | Maxim DS33Z41 specs

DS33Z41 Quad IMUX Ethernet Mapper

Figure 11-9. Receive IBO Channel Interleave Mode Timing

LINK #1, CHANNEL #1

RSYNC

RSER

L3 C32

L4 C32

L1 C1

L2 C1

L3 C1

L4 C1

L1 C2

L2 C2

L3 C2

L4 C2

BIT LEVEL DETAIL

RCLKI

RSYNC

	LINK 4, CHANNEL 32	LINK 1, CHANNEL 1		LINK 2, CHANNEL 1
RSER	LSB	MSB	LSB MSB	LSB
RSER

Note 1: 8.192MHz bus configuration.

Note 2: Data on unused channels must be filled with all ones.

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Image 153

Maxim DS33Z41 specifications Link #1, Channel #1 Rsync Rser, BIT Level Detail Rclki Rsync

Contents

Features Functional DiagramGeneral Description Applications Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights Sdram Interface Test and DiagnosticsMAC Interface Microprocessor Interface T1 Related Telecommunications Specifications Specifications compliance Quad T1/E1 SCT to DS33Z41 Time Slot Acronyms and Glossary Major Operating Modes Block Diagrams PIN Descriptions Name PIN Type Function Serial Interface IO PinsPin Functional Description Detailed Pin Descriptions MII/RMII Port Transmit Enable Rmii Transmit Enable MIIName PIN Type Function Transmit Data 0 through 1RMII. Two bits of data TXD MDC ColdetMdio Microprocessor Port Mode Control Name PIN Type Function Sdram Controller Jtag Interface Queue Status VDD3.3 Connect to 3.3V Power Supply Name PIN Type Function Power SuppliesVDD1.8 Connect to 1.8V Power Supply VSS Connect to the Common Supply Ground C D E F G H J K L M N DS33Z41 256-Ball Csbga Pinout Functional Description Read-Write/Data Strobe Modes Processor InterfaceClear on Read Interrupt and Pin Modes Clock Selection for the Ethernet LAN Interface Clock StructureRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN DTE Input Clocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock Modes Resets and Low-Power Modes Reset FunctionsReset Function Location Comments Global Resources Initialization and ConfigurationPer-Port Resources Example Device Initialization Sequence Device Interrupts Interrupt Pin Drawing Legend Link Aggregation Imux Serial Interface Sequence Imux Interface to T1/E1 Transceivers Microprocessor Requirements Commands Sent and Received on the Imux Links Imux Command ProtocolOOF Register Name Comments Command and Status for the Imux for Processor Communication Data Transfer Out of Frame OOF Monitoring Connections and Queues Registers Related to Connections and Queues ArbiterRegister Function Option Mode Flow ControlOptions for Flow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow control Ieee 802.3 Ethernet Frame Ethernet Interface Port Registers Related to the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Control Registers Ethernet MACMAC Status Registers Address Register Description Rmii Mode MII Mode Bert Features BertPHY MII Management Block and Mdio Interface Repetitive Pattern Synchronization Receive Data InterfaceReceive Pattern Detection Prbs Synchronization Error Insertion Pattern MonitoringPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Device Registers Register Address MapBert Global Register Bit Map Register Bit MapsGlobal Register Bit Map Name Bert Register Bit Map Arbiter Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map Repc Rapc Rspc RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h Global Register Definitions GL.IDRLGL.IDRH GL.BLR GL.CR1 04h GL.RTCALGL.SRCALS Global Sdram Reference Clock Activity Latched Status GL.LIS GL.LIEGL.SIE GL.SIS GL.TRQIS GL.TRQIEGL.IBIE GL.IBIS GL.C1QPR GL.CON1 Available User Commands Value Comment GL.IMXCNGL.IMXC GL.IMXSIE GL.IMXSS GL.IMXDFD GL.IMXSLSGL.IMXDFEIE GL.IMXDFDELS Inverse MUX OOF Interrupt Enable GL.IMXOOFIE1Eh GL.IMXOOFLS GL.BISTENGL.BISTPF GL.SDMODE1 GL.SDMODE2GL.SDMODEWS Global Sdram Refresh Time Control GL.SDRFTC3Dh SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 Arbiter Register Bit Descriptions Arbiter RegistersAR.RQSC1 AR.TQSC1 Bert Control Register Bert Registers80h Bit 7 This bit must be kept low for proper operation Bert Pattern Configuration High Register Bert Pattern Configuration Low Register82h 83h 84h Bert Pattern Byte 0 RegisterBert Pattern Byte 1 Register 85h 88h Transmit Error Insertion Control RegisterBert Status Register 8Ch Bert Status Register Latched Bert Status Register Interrupt Enable8Eh 90h RBECR2 99h Receive Bit Count Byte 1 Register #1Receive Bit Count Byte 2 Register 9Ah Serial Interface Transmit and Common Registers Serial Interface RegistersSerial Interface Transmit Register Bit Descriptions LI.RSTPD LI.TPPCL Transmit Hdlc Processor RegistersTransmit Packet Processor Control Low Register 0C4h LI.TEPLC LI.TIFGC Cleanup routine Transmit Errored Packet High Control RegisterLI.TEPHC 0C7h LI.TPPSR LI.TPPSRLLI.TPPSRIE LI.TPCR0 LI.TPCR1LI.TPCR2 LI.TBCR1 LI.TBCR0LI.TBCR2 LI.TBCR3 LI.THPMUS LI.THPMUU LI.TX86EDE 4 X.86 RegistersLI.TRX86A LI.TRX8C LI.CIR LI.TRX86SAPIL Receive Serial Interface LI.RPPCLLI.RMPSCL LI.RPPSR LI.RMPSCH LI.RPPSRL Receive Packet Processor Status Register Latched105h Receive Packet Processor Status Register Interrupt Enable LI.RPPSRIE106h LI.RPCB0 LI.RPCB1LI.RPCB2 LI.RFPCB0 LI.RFPCB1LI.RFPCB2 LI.RAPCB0 LI.RAPCB1LI.RAPCB2 LI.RSPCB0 LI.RSPCB1LI.RSPCB2 LI.RBC1 LI.RBC0LI.RBC2 LI.RBC3 LI.RAC1 LI.RAC0LI.RAC2 LI.RAC3 LI.RHPMUU LI.RHPMUSLI.RX86S LI.TQLT LI.RX86LSIE LI.TQHT LI.TQTIELI.TQCTLS Ethernet Interface Register Bit Descriptions Ethernet Interface RegistersSU.MACRADL SU.MACRADH SU.MACRD2 SU.MACRD1SU.MACRD3 SU.MACWD0 SU.MACWD2 SU.MACWD1SU.MACWD3 SU.MACAWL SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Transmit Frame Resend Control SU.TFRC151h Ncfq Tprhbc Tprcb SU.TFSH SU.TFSL SU.RFSB0 SU.RFSB1SU.RFSB2 SU.RFSB3 157hMCF SU.RMFSRH SU.RMFSRLSU.RQLT SU.RQHT SU.QCRLS SU.QRIE Receive Frame Rejection Control SU.RFRC15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACAL SU.MACAH SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Ch indirect MAC Reserved Control Register010Dh 010Eh 0111h 0110h indirect0112h 0113h MAC All Frames Received Counter SU.RxFrmCtr0200h indirect 0201h MAC Frames Received OK Counter SU.RxFrmOkCtr0204h indirect 0205h MAC All Frames Transmitted Counter SU.TxFrmCtr0300h indirect 0301h MAC All Bytes Transmitted Counter SU.TxBytesCtr0308h indirect 0309h MAC Bytes Transmitted OK Counter SU.TxBytesOkCtr030Ch indirect 030Dh SU.TXFRMUNDR MAC All Frames Aborted Counter SU.TxBdFrmCtr0338h indirect 0339h MII and Rmii Interfaces Functional Timing MII Receive Functional Timing Parameter Symbol Conditions MIN TYP MAX Units DC Electrical CharacteristicsOperating Parameters Recommended DC Operating Conditions Theta-JA vs. Airflow Thermal Characteristics -3. Thermal CharacteristicsParameter MIN TYP MAX AIR Flow THETA-JA MII Interface Transmit MII Interface Parameter Symbol10Mbps 100Mbps MIN TYP MAX Receive MII Interface Timing Receive MII Interface Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface Parameter Symbol MIN TYP MAX Units Mdio Interface -9. Mdio InterfaceMDC Mdio Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rser Rsync Receive WAN Interface 11. Receive WAN Interface Sdram Timing 12. Sdram Interface Timing 100MHzSdclko to SRAS, SCAS, SWE, Sdcs SRAS, Scas Sdata BIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing Diagram Jtag Information Jtag Functional Block Diagram Jtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State Diagram Instruction Codes for Ieee 1149.1 Architecture Test Registers Jtag ID Codes ID Code StructureBoundary Scan Register Bypass Register Jtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package Information Revision Description Document Revision History