Rmii Interface Transmit Rmii Interface | Maxim DS33Z41 instruction

DS33Z41 Quad IMUX Ethernet Mapper

11.3 RMII Interface

Table 11-7. Transmit RMII Interface

	PARAMETER	SYMBOL		10Mbps			100Mbps		UNITS
	PARAMETER	SYMBOL	MIN	TYP	MAX	MIN	TYP	MAX	UNITS
			MIN	TYP	MAX	MIN	TYP	MAX
	REF_CLK Frequency			50MHz			50MHz
	REF_CLK Frequency			±50ppm			±50ppm
				±50ppm			±50ppm
	REF_CLK Period	t1		20			20		ns
	REF_CLK Low Time	t2	7		13	7		13	ns
	REF_CLK High Time	t3	7		13	7		13	ns
	REF_CLK to TXD,	t4	5		10	5		10	ns
	TX_EN Delay	t4	5		10	5		10	ns
	TX_EN Delay

Figure 11-3. Transmit RMII Interface

	t1
REF_CLK	t2
REF_CLK	t3
	t4
TXD[1:0]
TX_EN	t4
TX_EN

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Maxim DS33Z41 specifications Rmii Interface Transmit Rmii Interface

Contents

General Description Functional DiagramFeatures Applications Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights MAC Interface Test and DiagnosticsSdram Interface Microprocessor Interface Specifications compliance T1 Related Telecommunications Specifications Quad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time Slot Block Diagrams Major Operating Modes Pin Functional Description Detailed Pin Descriptions Name PIN Type Function Serial Interface IO PinsPIN Descriptions MII/RMII Port Name PIN Type Function Transmit Enable MIITransmit Enable Rmii Transmit Data 0 through 1RMII. Two bits of data TXD Mdio ColdetMDC Microprocessor Port Mode Control Name PIN Type Function Sdram Controller Queue Status Jtag Interface VDD1.8 Connect to 1.8V Power Supply Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VSS Connect to the Common Supply Ground DS33Z41 256-Ball Csbga Pinout C D E F G H J K L M N Functional Description Clear on Read Processor InterfaceRead-Write/Data Strobe Modes Interrupt and Pin Modes Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clock StructureClock Selection for the Ethernet LAN Interface DTE Input Clocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Function Location Comments Resets and Low-Power ModesReset Functions Per-Port Resources Initialization and ConfigurationGlobal Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Interrupt Pin Serial Interface Link Aggregation Imux Imux Interface to T1/E1 Transceivers Sequence Microprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Command and Status for the Imux for Processor Communication Register Name Comments Out of Frame OOF Monitoring Data Transfer Connections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow control Ethernet Interface Port Ieee 802.3 Ethernet Frame DTE and DCE Mode Registers Related to the Ethernet Port Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Status Registers Ethernet MACMAC Control Registers Address Register Description MII Mode Rmii Mode PHY MII Management Block and Mdio Interface Bert FeaturesBert Receive Pattern Detection Receive Data InterfaceRepetitive Pattern Synchronization Prbs Synchronization Pattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Global Register Bit Map Register Bit MapsGlobal Register Bit Map Name Arbiter Register Bit Map Arbiter Register Bit MapBert Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h GL.IDRH Global Register DefinitionsGL.IDRL GL.CR1 GL.BLR GL.SRCALS GL.RTCAL04h Global Sdram Reference Clock Activity Latched Status GL.SIE GL.LIEGL.LIS GL.SIS GL.IBIE GL.TRQIEGL.TRQIS GL.IBIS GL.CON1 GL.C1QPR GL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSS GL.IMXSIE GL.IMXDFEIE GL.IMXSLSGL.IMXDFD GL.IMXDFDELS 1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 3Dh GL.SDRFTCGlobal Sdram Refresh Time Control SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 AR.RQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.TQSC1 80h Bert RegistersBert Control Register Bit 7 This bit must be kept low for proper operation 82h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 83h Bert Pattern Byte 1 Register Bert Pattern Byte 0 Register84h 85h Bert Status Register Transmit Error Insertion Control Register88h 8Ch 8Eh Bert Status Register Interrupt EnableBert Status Register Latched 90h RBECR2 Receive Bit Count Byte 2 Register Receive Bit Count Byte 1 Register #199h 9Ah Serial Interface Transmit Register Bit Descriptions Serial Interface RegistersSerial Interface Transmit and Common Registers LI.RSTPD Transmit Packet Processor Control Low Register Transmit Hdlc Processor RegistersLI.TPPCL 0C4h LI.TIFGC LI.TEPLC LI.TEPHC Transmit Errored Packet High Control RegisterCleanup routine 0C7h LI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR2 LI.TBCR0LI.TBCR1 LI.TBCR3 LI.THPMUU LI.THPMUS LI.TRX86A 4 X.86 RegistersLI.TX86EDE LI.TRX8C LI.TRX86SAPIL LI.CIR LI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RPPSR 105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC2 LI.RBC0LI.RBC1 LI.RBC3 LI.RAC2 LI.RAC0LI.RAC1 LI.RAC3 LI.RX86S LI.RHPMUULI.RHPMUS LI.RX86LSIE LI.TQLT LI.TQCTLS LI.TQHTLI.TQTIE SU.MACRADL Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADH SU.MACRD3 SU.MACRD1SU.MACRD2 SU.MACWD0 SU.MACWD3 SU.MACWD1SU.MACWD2 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR 151h SU.TFRCTransmit Frame Resend Control Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RQLT SU.RMFSRLSU.RMFSRH SU.RQHT SU.QRIE SU.QCRLS 15Eh SU.RFRCReceive Frame Rejection Control Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACAH SU.MACAL SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh MAC Reserved Control Register010Ch indirect 010Eh 0112h 0110h indirect0111h 0113h 0200h indirect SU.RxFrmCtrMAC All Frames Received Counter 0201h 0204h indirect SU.RxFrmOkCtrMAC Frames Received OK Counter 0205h 0300h indirect SU.TxFrmCtrMAC All Frames Transmitted Counter 0301h 0308h indirect SU.TxBytesCtrMAC All Bytes Transmitted Counter 0309h 030Ch indirect SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Dh SU.TXFRMUNDR 0338h indirect SU.TxBdFrmCtrMAC All Frames Aborted Counter 0339h Functional Timing MII and Rmii Interfaces MII Receive Functional Timing Operating Parameters DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Recommended DC Operating Conditions Parameter MIN TYP MAX Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow AIR Flow THETA-JA 10Mbps 100Mbps Parameter SymbolMII Interface Transmit MII Interface MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface Timing MDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser Tsync Receive WAN Interface 11. Receive WAN Interface Rclki Rser Rsync Sdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz Sdata SRAS, Scas Link #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface Timing Jtag Functional Block Diagram Jtag Information Jtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Boundary Scan Register Jtag ID Codes ID Code StructureTest Registers Bypass Register Jtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Document Revision History Revision Description