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Maxim DS33Z41 specifications MAC Indirect Register Bit Map, MAC Register Bit Map

Models: DS33Z41

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DS33Z41 Quad IMUX Ethernet Mapper

9.1.6MAC Register Bit Map

Table 9-7. MAC Indirect Register Bit Map

ADDR	NAME	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
0000h	SU.MACCR	-	-	-	HDB	PS	-	-	-
0000h	31:24
	31:24
0001h	23:16	DRO	OML1	OML0	F	PM	PAM	-	-
0002h	15:8	-	-	-	LCC	-	DRTY	-	ASTP
0003h	7:0	BOLMT1	BOLMT0	DC	-	TE	RE	-	-
0004h	SU.MACAH	-	-	-	-	-	-	-	-
0004h	31:24
	31:24
0005h	23:16	-	-	-	-	-	-	-	-
0006h	15:8	PADR47	PADR46	PADR45	PADR44	PADR43	PADR42	PADR41	PADR40
0007h	7:0	PADR39	PADR38	PADR37	PADR36	PADR35	PADR34	PADR33	PADR32
0008h	SU.MACAL	PADR31	PADR30	PADR29	PADR28	PADR27	PADR26	PADR25	PADR24
0008h	31:24
	31:24
0009h	23:16	PADR23	PADR22	PADR21	PADR20	PADR19	PADR18	PADR17	PADR16
000Ah	15:8	PADR15	PADR14	PADR13	PADR12	PADR11	PADR10	PADR09	PADR08
000Bh	7:0	PADR07	PADR06	PADR05	PADR04	PADR03	PADR02	PADR01	PADR00
000Ch	Reserved	-	-	-	-	-	-	-	-
000Dh	Reserved	-	-	-	-	-	-	-	-
000Eh	Reserved	-	-	-	-	-	-	-	-
000Fh	Reserved	-	-	-	-	-	-	-	-
0010h	Reserved	-	-	-	-	-	-	-	-
0011h	Reserved	-	-	-	-	-	-	-	-
0012h	Reserved	-	-	-	-	-	-	-	-
0013h	Reserved	-	-	-	-	-	-	-	-
0014h	SU.MACMIIA	-	-	-	-	-	-	-	-
	31:24
0015h	23:16	-	-	-	-	-	-	-	-
0016h	15:8	PHYA4	PHYA3	PHYA2	PHYA1	PHYA0	MIIA4	MIIA3	MIIA2
0017h	7:0	MIIA1	MIIA0	-	-	-	-	MIIW	MIIB
0018h	SU.MACMIID	-	-	-	-	-	-	-	-
	31:24
0019h	23:16	-	-	-	-	-	-	-	-
001Ah	15:8	MIID15	MIID14	MIID13	MIID12	MIID11	MIID10	MIID09	MIID08
001Bh	7:0	MIID07	MIID06	MIID05	MIID04	MIID03	MIID02	MIID01	MIID00
001Ch	SU.MACFCR	PT15	PT14	PT13	PT12	PT11	PT10	PT09	PT08
	31:24
001Dh	23:16	PT07	PT06	PT05	PT04	PT03	PT02	PT01	PT00
001Eh	15:8	-	-	-	-	-	-	-	-
001Fh	7:0	-	-	-	-	-	PCF	FCE	FCB
100h	SU.MMCCTRL	-	-	-	-	-	-	-	-
	31:24
101h	23:16	-	-	-	-	-	-	-	-
102h	15:8	-	-	MXFRM10	MXFRM9	MXFRM8	MXFRM7	MXFRM6	MXFRM5
103h	7:0	MXFRM4	MXFRM3	MXFRM2	MXFRM1	MXFRM0	-	-	-
10Ch	RESERVED –	-	-	-	-	-	-	-	-
	initialize to FF
10Dh	RESERVED –	-	-	-	-	-	-	-	-
	initialize to FF
10Eh	RESERVED –	-	-	-	-	-	-	-	-
	initialize to FF
10Fh	RESERVED –	-	-	-	-	-	-	-	-
	initialize to FF
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Maxim DS33Z41 specifications MAC Indirect Register Bit Map, MAC Register Bit Map

Contents

General Description Functional DiagramFeatures ApplicationsTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights MAC Interface Test and DiagnosticsSdram Interface Microprocessor InterfaceSpecifications compliance T1 Related Telecommunications SpecificationsQuad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time SlotBlock Diagrams Major Operating ModesPin Functional Description Detailed Pin Descriptions Name PIN Type Function Serial Interface IO PinsPIN Descriptions MII/RMII PortName PIN Type Function Transmit Enable MIITransmit Enable Rmii Transmit Data 0 through 1RMII. Two bits of data TXDMdio ColdetMDC Microprocessor PortMode Control Name PIN Type Function Sdram Controller Queue Status Jtag InterfaceVDD1.8 Connect to 1.8V Power Supply Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VSS Connect to the Common Supply GroundDS33Z41 256-Ball Csbga Pinout C D E F G H J K L M NFunctional Description Clear on Read Processor InterfaceRead-Write/Data Strobe Modes Interrupt and Pin ModesRmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clock StructureClock Selection for the Ethernet LAN Interface DTE InputClocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock ModesResets and Low-Power Modes Reset FunctionsReset Function Location Comments Per-Port Resources Initialization and ConfigurationGlobal Resources Example Device Initialization SequenceDevice Interrupts Drawing Legend Interrupt PinSerial Interface Link Aggregation ImuxImux Interface to T1/E1 Transceivers SequenceMicroprocessor Requirements Commands Sent and Received on the Imux Links Imux Command ProtocolOOF Command and Status for the Imux for Processor Communication Register Name CommentsOut of Frame OOF Monitoring Data TransferConnections and Queues Registers Related to Connections and Queues ArbiterRegister Function Option Mode Flow ControlOptions for Flow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow controlEthernet Interface Port Ieee 802.3 Ethernet FrameDTE and DCE Mode Registers Related to the Ethernet PortConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Status Registers Ethernet MACMAC Control Registers Address Register DescriptionMII Mode Rmii ModeBert Features BertPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfaceRepetitive Pattern Synchronization Prbs SynchronizationError Insertion Pattern MonitoringPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Device Registers Register Address MapBert Global Register Bit Map Register Bit MapsGlobal Register Bit Map NameArbiter Register Bit Map Arbiter Register Bit MapBert Register Bit Map Bert Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRepl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie RspcieEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Indirect Register Bit Map MAC Register Bit Map200h Global Register Definitions GL.IDRLGL.IDRH GL.CR1 GL.BLRGL.SRCALS GL.RTCAL04h Global Sdram Reference Clock Activity Latched StatusGL.SIE GL.LIEGL.LIS GL.SISGL.IBIE GL.TRQIEGL.TRQIS GL.IBISGL.CON1 GL.C1QPRAvailable User Commands Value Comment GL.IMXCNGL.IMXC GL.IMXSS GL.IMXSIEGL.IMXDFEIE GL.IMXSLSGL.IMXDFD GL.IMXDFDELSInverse MUX OOF Interrupt Enable GL.IMXOOFIE1Eh GL.IMXOOFLS GL.BISTENGL.BISTPF GL.SDMODE1 GL.SDMODE2GL.SDMODEWS 3Dh GL.SDRFTCGlobal Sdram Refresh Time Control SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0AR.RQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.TQSC180h Bert RegistersBert Control Register Bit 7 This bit must be kept low for proper operation82h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 83hBert Pattern Byte 1 Register Bert Pattern Byte 0 Register84h 85hBert Status Register Transmit Error Insertion Control Register88h 8Ch8Eh Bert Status Register Interrupt EnableBert Status Register Latched 90hRBECR2 Receive Bit Count Byte 2 Register Receive Bit Count Byte 1 Register #199h 9AhSerial Interface Transmit Register Bit Descriptions Serial Interface RegistersSerial Interface Transmit and Common Registers LI.RSTPDTransmit Packet Processor Control Low Register Transmit Hdlc Processor RegistersLI.TPPCL 0C4hLI.TIFGC LI.TEPLCLI.TEPHC Transmit Errored Packet High Control RegisterCleanup routine 0C7hLI.TPPSR LI.TPPSRLLI.TPPSRIE LI.TPCR0 LI.TPCR1LI.TPCR2 LI.TBCR2 LI.TBCR0LI.TBCR1 LI.TBCR3LI.THPMUU LI.THPMUSLI.TRX86A 4 X.86 RegistersLI.TX86EDE LI.TRX8CLI.TRX86SAPIL LI.CIRReceive Serial Interface LI.RPPCLLI.RMPSCL LI.RMPSCH LI.RPPSRLI.RPPSRL Receive Packet Processor Status Register Latched105h Receive Packet Processor Status Register Interrupt Enable LI.RPPSRIE106h LI.RPCB0 LI.RPCB1LI.RPCB2 LI.RFPCB0 LI.RFPCB1LI.RFPCB2 LI.RAPCB0 LI.RAPCB1LI.RAPCB2 LI.RSPCB0 LI.RSPCB1LI.RSPCB2 LI.RBC2 LI.RBC0LI.RBC1 LI.RBC3LI.RAC2 LI.RAC0LI.RAC1 LI.RAC3LI.RHPMUU LI.RHPMUSLI.RX86S LI.RX86LSIE LI.TQLTLI.TQHT LI.TQTIELI.TQCTLS SU.MACRADL Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADHSU.MACRD3 SU.MACRD1SU.MACRD2 SU.MACWD0SU.MACWD3 SU.MACWD1SU.MACWD2 SU.MACAWLSU.MACAWH SU.MACRWCSU.LPBK SU.GCR151h SU.TFRCTransmit Frame Resend Control Ncfq Tprhbc TprcbSU.TFSL SU.TFSHSU.RFSB0 SU.RFSB1SU.RFSB2 SU.RFSB3 157hMCF SU.RQLT SU.RMFSRLSU.RMFSRH SU.RQHTSU.QRIE SU.QCRLS15Eh SU.RFRCReceive Frame Rejection Control Ucfr Cfrr Lerr Crcerr DBR Miier BFRMAC Registers SU.MACCRBit Random Number Generator Bits Used SU.MACAH SU.MACALSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh MAC Reserved Control Register010Ch indirect 010Eh0112h 0110h indirect0111h 0113h0200h indirect SU.RxFrmCtrMAC All Frames Received Counter 0201h0204h indirect SU.RxFrmOkCtrMAC Frames Received OK Counter 0205h0300h indirect SU.TxFrmCtrMAC All Frames Transmitted Counter 0301h0308h indirect SU.TxBytesCtrMAC All Bytes Transmitted Counter 0309h030Ch indirect SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030DhSU.TXFRMUNDR 0338h indirect SU.TxBdFrmCtrMAC All Frames Aborted Counter 0339hFunctional Timing MII and Rmii InterfacesMII Receive Functional Timing Operating Parameters DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Recommended DC Operating ConditionsParameter MIN TYP MAX Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow AIR Flow THETA-JA10Mbps 100Mbps Parameter SymbolMII Interface Transmit MII Interface MIN TYP MAXReceive MII Interface Receive MII Interface TimingRmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface TimingParameter Symbol MIN TYP MAX Units Mdio Interface -9. Mdio InterfaceMDC Mdio Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser TsyncReceive WAN Interface 11. Receive WAN Interface Rclki Rser RsyncSdram Timing 12. Sdram Interface Timing 100MHzSdclko to SRAS, SCAS, SWE, Sdcs Sdata SRAS, ScasLink #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface TimingJtag Functional Block Diagram Jtag InformationJtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction RegisterInstruction Codes for Ieee 1149.1 Architecture Boundary Scan Register Jtag ID Codes ID Code StructureTest Registers Bypass RegisterJtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001Document Revision History Revision Description