Quad T1/E1 SCT to DS33Z41 | Maxim instruction

DS33Z41 Quad IMUX Ethernet Mapper

3APPLICATIONS

•Bonded Transparent LAN Service

•LAN Extension

•Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4

Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design.

Figure 3-1. Quad T1/E1 SCT to DS33Z41

HDLC/X.86

Serial

T1/E1 Stream

Framer/LIU (IBO) DS21455

DS21458

DS26528

DS33Z41

RMII, MII

10 Base T

100 Base T

Ethernet

SDRAM

Clock

Sources

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Image 11

Maxim specifications Quad T1/E1 SCT to DS33Z41

Contents

Applications Functional DiagramFeatures General Description Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights Microprocessor Interface Test and DiagnosticsSdram Interface MAC Interface T1 Related Telecommunications Specifications Specifications compliance Quad T1/E1 SCT to DS33Z41 Time Slot Acronyms and Glossary Major Operating Modes Block Diagrams MII/RMII Port Name PIN Type Function Serial Interface IO PinsPIN Descriptions Pin Functional Description Detailed Pin Descriptions Transmit Data 0 through 1RMII. Two bits of data TXD Transmit Enable MIITransmit Enable Rmii Name PIN Type Function Microprocessor Port ColdetMDC Mdio Mode Control Name PIN Type Function Sdram Controller Jtag Interface Queue Status VSS Connect to the Common Supply Ground Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VDD1.8 Connect to 1.8V Power Supply C D E F G H J K L M N DS33Z41 256-Ball Csbga Pinout Functional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on Read DTE Input Clock StructureClock Selection for the Ethernet LAN Interface Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock Modes Reset Function Location Comments Resets and Low-Power ModesReset Functions Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port Resources Device Interrupts Interrupt Pin Drawing Legend Link Aggregation Imux Serial Interface Sequence Imux Interface to T1/E1 Transceivers Microprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Register Name Comments Command and Status for the Imux for Processor Communication Data Transfer Out of Frame OOF Monitoring Connections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow control Ieee 802.3 Ethernet Frame Ethernet Interface Port Registers Related to the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Address Register Description Ethernet MACMAC Control Registers MAC Status Registers Rmii Mode MII Mode PHY MII Management Block and Mdio Interface Bert FeaturesBert Prbs Synchronization Receive Data InterfaceRepetitive Pattern Synchronization Receive Pattern Detection Pattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Name Register Bit MapsGlobal Register Bit Map Global Register Bit Map Bert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h GL.IDRH Global Register DefinitionsGL.IDRL GL.BLR GL.CR1 Global Sdram Reference Clock Activity Latched Status GL.RTCAL04h GL.SRCALS GL.SIS GL.LIEGL.LIS GL.SIE GL.IBIS GL.TRQIEGL.TRQIS GL.IBIE GL.C1QPR GL.CON1 GL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSIE GL.IMXSS GL.IMXDFDELS GL.IMXSLSGL.IMXDFD GL.IMXDFEIE 1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 GL.SDRFTCGlobal Sdram Refresh Time Control 3Dh AR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC1 Bit 7 This bit must be kept low for proper operation Bert RegistersBert Control Register 80h 83h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 82h 85h Bert Pattern Byte 0 Register84h Bert Pattern Byte 1 Register 8Ch Transmit Error Insertion Control Register88h Bert Status Register 90h Bert Status Register Interrupt EnableBert Status Register Latched 8Eh RBECR2 9Ah Receive Bit Count Byte 1 Register #199h Receive Bit Count Byte 2 Register LI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers Serial Interface Transmit Register Bit Descriptions 0C4h Transmit Hdlc Processor RegistersLI.TPPCL Transmit Packet Processor Control Low Register LI.TEPLC LI.TIFGC 0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHC LI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2 LI.THPMUS LI.THPMUU LI.TRX8C 4 X.86 RegistersLI.TX86EDE LI.TRX86A LI.CIR LI.TRX86SAPIL LI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RPPSR LI.RMPSCH 105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2 LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2 LI.RX86S LI.RHPMUULI.RHPMUS LI.TQLT LI.RX86LSIE LI.TQCTLS LI.TQHTLI.TQTIE SU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADL SU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3 SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3 SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Ncfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151h SU.TFSH SU.TFSL SU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLT SU.QCRLS SU.QRIE Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15Eh SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACAL SU.MACAH SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Eh MAC Reserved Control Register010Ch indirect 010Dh 0113h 0110h indirect0111h 0112h 0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect 0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect 0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect 0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect 030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirect SU.TXFRMUNDR 0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirect MII and Rmii Interfaces Functional Timing MII Receive Functional Timing Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Operating Parameters AIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAX MIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100Mbps Receive MII Interface Timing Receive MII Interface Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface MDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rser Rsync Receive WAN Interface 11. Receive WAN Interface Sdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz SRAS, Scas Sdata BIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing Diagram Jtag Information Jtag Functional Block Diagram Jtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State Diagram Instruction Codes for Ieee 1149.1 Architecture Bypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan Register Jtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package Information Revision Description Document Revision History