
DS33Z41 Quad IMUX Ethernet Mapper
8.2.1Serial Interface Clock Modes
The Serial Interface timing is determined by the line clocks. 8.192MHz is the required clock rate for interfacing the IBO bus to Dallas Semiconductor Framers and
8.2.2Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation. Table
In RMII mode, receive and transmit timing is always synchronous to a 50MHz clock input on the REF_CLK pin. The source of REF_CLK is expected to be the external PHY. More information on RMII mode can be found in Section 8.14.2.
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and RX_CLK) are output by the DS33Z41, and are derived from the 25MHz REF_CLK input. More information on MII mode can be found in Section 8.14.1.
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