Maxim DS33Z41 specifications List of Tables

DS33Z41 Quad IMUX Ethernet Mapper
LIST OF TABLES
Table 2-1. T1 Related Telecommunications Specifications	10
Table 7-1. Detailed Pin Descriptions	14
Table 8-1. Clock Selection for the Ethernet (LAN) Interface	24
Table 8-2. Reset Functions	27
Table 8-3. Commands Sent and Received on the IMUX Links	34
Table 8-4. Command and Status for the IMUX for Processor Communication	35
Table 8-5. Registers Related to Connections and Queues	38
Table 8-6. Options for Flow Control	39
Table 8-7. Registers Related to the Ethernet Port	43
Table 8-8. MAC Control Registers	46
Table 8-9. MAC Status Registers	46
Table 9-1. Register Address Map	60
Table 9-2. Global Register Bit Map	61
Table 9-3. Arbiter Register Bit Map	62
Table 9-4. BERT Register Bit Map	62
Table 9-5. Serial Interface Register Bit Map	63
Table 9-6. Ethernet Interface Register Bit Map	65
Table 9-7. MAC Indirect Register Bit Map	66
Table 11-1. Recommended DC Operating Conditions	142
Table 11-2. DC Electrical Characteristics	142
Table 11-3. Thermal Characteristics	143
Table 11-4. Theta-JA vs. Airflow	143
Table 11-5. Transmit MII Interface	144
Table 11-6. Receive MII Interface	145
Table 11-7. Transmit RMII Interface	146
Table 11-8. Receive RMII Interface	147
Table 11-9. MDIO Interface	148
Table 11-10. Transmit WAN Interface	149
Table 11-11. Receive WAN Interface	150
Table 11-12. SDRAM Interface Timing	151
Table 11-13. AC Characteristics—Microprocessor Bus Timing	155
Table 11-14. JTAG Interface Timing	158
Table 12-1. Instruction Codes for IEEE 1149.1 Architecture	163
Table 12-2. ID Code Structure	164

6 of 167