DS33Z41 Quad IMUX Ethernet Mapper
14 DOCUMENT REVISION HISTORY
REVISION | DESCRIPTION | |
021405 | New Product Release | |
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| |
| Added TCLKI to TSER Output Delay Minimum of 3ns. | |
| Added TCLKI to TSYNC Setup Time Minimum of 3.5ns. | |
| Added definition for BPCLR.PLF[4:0]. | |
| Corrected pin description of MDC. | |
| Corrected default value listed in the SU.RMFSRL register definition. | |
| Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC register | |
| definitions. | |
| Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC registers to the | |
| register bit map. | |
| Clarified the GL.C1QPR register definition. | |
| Corrected SU.MACCR.PM and SU.MACCR.PAM bit definitions. | |
| Corrected pin description of RST. | |
122006 | Corrected pin description of REF_CLK. | |
Clarified text regarding use of REF_CLKO in DCE and RMII modes. | ||
| ||
| Corrected SU.GCR.H10S bit definition. | |
| Corrected the SU.RQLT and SU.RQHT default values to zero. | |
| Corrected SU.MACCR register definition. | |
| Removed a reference to SPI and EEPROM mode. | |
| Clarified section 8.19 on X.86 mode synchronization. | |
| Corrected | |
| Added D/C operating current maximum values. | |
| Updated D/C operating current typical values. | |
| Added D/C Characteristic entries for Supply currents in “standby” conditions. | |
| Corrected the link start command value in the GL.IMXC register definition. | |
| Clarified RSER conditions for unused input time slots. | |
| Updated package drawing. |
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