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Maxim DS33Z41 specifications GL.SDMODE1, GL.SDMODE2, Gl.Sdmodews

Models: DS33Z41

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DS33Z41 Quad IMUX Ethernet Mapper

Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the SDRAM and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z41.

Register Name:				GL.SDMODE1
Register Description:				Global SDRAM Mode Register 1
Register Address:				3Ah
Bit #		7	6	5		4	3	2	1	0
Name		—	—		—	—	WT	BL2	BL1	BL0
Default		0	0		0	0	0	0	1	1

Bit 3: Wrap Type (WT). This bit is used to configure the wrap mode.

0 = Sequential

1 = Interleave

Bits 2 to 0: Burst Length 2 to 0 (BL2 to BL0). These bits are used to determine the burst length.

Note: This register has a non-zero default value. This should be taken into consideration when initializing the device.

Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to write the new values to the SDRAM.

Register Name:				GL.SDMODE2
Register Description:				Global SDRAM Mode Register 2
Register Address:				3Bh
Bit #		7	6	5		4		3	2	1	0
Name		—	—		—	—		—	LTMOD2	LTMOD1	LTMOD0
Default		0	0		0	0		0	0	1	0

Bits 2 to 0: CAS Latency Mode (LTMOD2 to LTMOD0). These bits are used to set up CAS latency. Note: Only CAS latency of 2 or 3 is allowed.

Note: This register has a non-zero default value. This should be taken into consideration when initializing the device.

Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to write the new values to the SDRAM.

Register Name:				GL.SDMODEWS
Register Description:				Global SDRAM Mode Register Write Status
Register Address:				3Ch
Bit #		7	6	5			4	3		2	1	0
Name		—	—		—		—	—		—	—	SDMW
Default		0	0		0		0	0		0	0	0

Bit 0: SDRAM Mode Write (SDMW). Setting this bit to 1 will write the current values of the mode control and refresh time control registers to the SDRAM. The user must clear this bit and set it again for subsequent write operations.

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Maxim DS33Z41 specifications GL.SDMODE1, GL.SDMODE2, Gl.Sdmodews

Contents

Applications Functional DiagramFeatures General DescriptionTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights Microprocessor Interface Test and DiagnosticsSdram Interface MAC InterfaceT1 Related Telecommunications Specifications Specifications complianceQuad T1/E1 SCT to DS33Z41 Time Slot Acronyms and GlossaryMajor Operating Modes Block DiagramsMII/RMII Port Name PIN Type Function Serial Interface IO PinsPIN Descriptions Pin Functional Description Detailed Pin DescriptionsTransmit Data 0 through 1RMII. Two bits of data TXD Transmit Enable MIITransmit Enable Rmii Name PIN Type FunctionMicroprocessor Port ColdetMDC MdioMode Control Name PIN Type Function Sdram Controller Jtag Interface Queue StatusVSS Connect to the Common Supply Ground Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VDD1.8 Connect to 1.8V Power SupplyC D E F G H J K L M N DS33Z41 256-Ball Csbga PinoutFunctional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on ReadDTE Input Clock StructureClock Selection for the Ethernet LAN Interface Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PINClocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock ModesReset Functions Resets and Low-Power ModesReset Function Location Comments Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port ResourcesDevice Interrupts Interrupt Pin Drawing LegendLink Aggregation Imux Serial InterfaceSequence Imux Interface to T1/E1 TransceiversMicroprocessor Requirements Imux Command Protocol Commands Sent and Received on the Imux LinksOOF Register Name Comments Command and Status for the Imux for Processor CommunicationData Transfer Out of Frame OOF MonitoringConnections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Option ModeOptions for Flow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow controlIeee 802.3 Ethernet Frame Ethernet Interface PortRegisters Related to the Ethernet Port DTE and DCE ModeConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Address Register Description Ethernet MACMAC Control Registers MAC Status RegistersRmii Mode MII ModeBert Bert FeaturesPHY MII Management Block and Mdio Interface Prbs Synchronization Receive Data InterfaceRepetitive Pattern Synchronization Receive Pattern DetectionPattern Monitoring Error InsertionPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Register Address Map Device RegistersBert Name Register Bit MapsGlobal Register Bit Map Global Register Bit MapBert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRepie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl RspclEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Register Bit Map MAC Indirect Register Bit Map200h GL.IDRL Global Register DefinitionsGL.IDRH GL.BLR GL.CR1Global Sdram Reference Clock Activity Latched Status GL.RTCAL04h GL.SRCALSGL.SIS GL.LIEGL.LIS GL.SIEGL.IBIS GL.TRQIEGL.TRQIS GL.IBIEGL.C1QPR GL.CON1GL.IMXCN Available User Commands Value CommentGL.IMXC GL.IMXSIE GL.IMXSSGL.IMXDFDELS GL.IMXSLSGL.IMXDFD GL.IMXDFEIEGL.IMXOOFIE Inverse MUX OOF Interrupt Enable1Eh GL.BISTEN GL.IMXOOFLSGL.BISTPF GL.SDMODE2 GL.SDMODE1GL.SDMODEWS SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 GL.SDRFTCGlobal Sdram Refresh Time Control 3DhAR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC1Bit 7 This bit must be kept low for proper operation Bert RegistersBert Control Register 80h83h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 82h85h Bert Pattern Byte 0 Register84h Bert Pattern Byte 1 Register8Ch Transmit Error Insertion Control Register88h Bert Status Register90h Bert Status Register Interrupt EnableBert Status Register Latched 8EhRBECR2 9Ah Receive Bit Count Byte 1 Register #199h Receive Bit Count Byte 2 RegisterLI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers Serial Interface Transmit Register Bit Descriptions0C4h Transmit Hdlc Processor RegistersLI.TPPCL Transmit Packet Processor Control Low RegisterLI.TEPLC LI.TIFGC0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHCLI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2LI.THPMUS LI.THPMUULI.TRX8C 4 X.86 RegistersLI.TX86EDE LI.TRX86ALI.CIR LI.TRX86SAPILLI.RPPCL Receive Serial InterfaceLI.RMPSCL LI.RPPSR LI.RMPSCHReceive Packet Processor Status Register Latched LI.RPPSRL105h LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2LI.RHPMUS LI.RHPMUULI.RX86S LI.TQLT LI.RX86LSIELI.TQTIE LI.TQHTLI.TQCTLS SU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADLSU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3SU.MACRWC SU.MACAWHSU.GCR SU.LPBKNcfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151hSU.TFSH SU.TFSLSU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLTSU.QCRLS SU.QRIEUcfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15EhSU.MACCR MAC RegistersBit Random Number Generator Bits Used SU.MACAL SU.MACAHSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Eh MAC Reserved Control Register010Ch indirect 010Dh0113h 0110h indirect0111h 0112h0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirectSU.TXFRMUNDR 0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirectMII and Rmii Interfaces Functional TimingMII Receive Functional Timing Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Operating ParametersAIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAXMIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100MbpsReceive MII Interface Timing Receive MII InterfaceRmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii InterfaceMdio Interface -9. Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN InterfaceRclki Rser Rsync Receive WAN Interface 11. Receive WAN Interface100MHz Sdram Timing 12. Sdram Interface TimingSdclko to SRAS, SCAS, SWE, Sdcs SRAS, Scas SdataBIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing DiagramJtag Information Jtag Functional Block DiagramJtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State DiagramInstruction Codes for Ieee 1149.1 Architecture Bypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan RegisterJtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package InformationRevision Description Document Revision History