
DS33Z41 Quad IMUX Ethernet Mapper
Figure 12-2. TAP Controller State Diagram
1 | Test Logic |
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Reset |
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| 0 | 1 |
| 1 |
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| 1 |
0 | Run Test/ | Select |
| Select | |||
Idle |
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| 1 | 0 |
| 1 | 0 |
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| Capture DR |
| Capture IR |
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| 0 |
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| 0 |
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| Shift DR | 0 |
| Shift IR | 0 | |
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| 1 |
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| 1 | 1 |
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| Exit DR | 1 |
| Exit IR | |
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| 0 |
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| 0 |
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| Pause DR | 0 | Pause IR | 0 | ||
0 |
| 1 |
| 0 | 1 |
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Exit2 DR |
| Exit2 IR |
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| 1 |
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| 1 |
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| Update DR |
| Update IR |
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| 1 | 0 |
| 1 | 0 |
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12.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the
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