Su.Tfsl, Su.Tfsh | Maxim DS33Z41 specs

DS33Z41 Quad IMUX Ethernet Mapper

Register Name:			SU.TFSL
Register Description:			Transmit Frame Status Low
Register Address:			152h
Bit #	7	6	5		4		3	2	1	0
Name	UR	EC		LC	ED		LOC	NOC	—	FABORT
Default	0	0		0	0		0	0	0	0

Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer.

Bit 6: Excessive Collisions (EC). When this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame. If the Disable Retry bit is set to 1, then Excessive Collisions will be set to 1 after the first collision.

Bit 5: Late Collision (LC). When this bit is set to 1, a frame was aborted by collision after the 64 bit collision window. Not valid if an under run has occurred.

Bit 4: Excessive Deferral (ED). When this bit is set to 1, a frame was aborted due to excessive deferral.

Bit 3: Loss Of Carrier (LOC). When this bit is set to 1, a frame was aborted due to loss of carrier for one or more bit times. Valid only for non-collided frames. Valid only in half-duplex operation.

Bit 2: No Carrier (NOC). When this bit is set to 1, a frame was aborted because no carrier was found for transmission.

Bit 0: Frame Abort (FABORT). When this bit is set to 1, the MAC has aborted a frame for one of the above reasons. When this bit is clear, the previous frame has been transmitted successfully.

Register Name:			SU.TFSH
Register Description:			Transmit Frame Status High
Register Address:			153h
Bit #	7	6	5		4		3	2	1	0
Name	PR	HBF		CC3	CC2		CC1	CC0	LCO	DEF
Default	0	0		0	0		0	0	0	0

Bit 7: Packet Resend (PR). When this bit is set, the current packet must be retransmitted due to a collision.

Bit 6: Heartbeat Failure (HBF). When this bit is set, the device failed to detect a heart beat after transmission. This bit is not valid if an under run has occurred.

Bits 5 to 2: Collision Count (CC3 to CC0). These 4 bits indicate the number of collisions that occurred prior to successful transmission of the previous frame. Not valid if Excessive Collisions is set to 1.

Bit 1: Late Collision (LCO). When set to 1, the MAC observed a collision after the 64-byte collision window.

Bit 0: Deferred Frame (DEF). When set to 1, the current frame was deferred due to carrier assertion by another node after being ready to transmit.

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Maxim DS33Z41 specifications Su.Tfsl, Su.Tfsh

Contents

General Description Functional DiagramFeatures Applications Table of Contents 140 166 List of Figures List of Tables Description Feature Highlights MAC Interface Test and DiagnosticsSdram Interface Microprocessor Interface Specifications compliance T1 Related Telecommunications Specifications Quad T1/E1 SCT to DS33Z41 Acronyms and Glossary Time Slot Block Diagrams Major Operating Modes Pin Functional Description Detailed Pin Descriptions Name PIN Type Function Serial Interface IO PinsPIN Descriptions MII/RMII Port Name PIN Type Function Transmit Enable MIITransmit Enable Rmii Transmit Data 0 through 1RMII. Two bits of data TXD Mdio ColdetMDC Microprocessor Port Mode Control Name PIN Type Function Sdram Controller Queue Status Jtag Interface VDD1.8 Connect to 1.8V Power Supply Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VSS Connect to the Common Supply Ground DS33Z41 256-Ball Csbga Pinout C D E F G H J K L M N Functional Description Clear on Read Processor InterfaceRead-Write/Data Strobe Modes Interrupt and Pin Modes Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PIN Clock StructureClock Selection for the Ethernet LAN Interface DTE Input Clocking for the DS33Z41 Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Functions Resets and Low-Power ModesReset Function Location Comments Per-Port Resources Initialization and ConfigurationGlobal Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Interrupt Pin Serial Interface Link Aggregation Imux Imux Interface to T1/E1 Transceivers Sequence Microprocessor Requirements Imux Command Protocol Commands Sent and Received on the Imux LinksOOF Command and Status for the Imux for Processor Communication Register Name Comments Out of Frame OOF Monitoring Data Transfer Connections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Option ModeOptions for Flow Control Full-Duplex Flow Control Half-Duplex Flow control Host-Managed Flow control Ethernet Interface Port Ieee 802.3 Ethernet Frame DTE and DCE Mode Registers Related to the Ethernet Port Configured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode MAC Status Registers Ethernet MACMAC Control Registers Address Register Description MII Mode Rmii Mode Bert Bert FeaturesPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfaceRepetitive Pattern Synchronization Prbs Synchronization Pattern Monitoring Error InsertionPattern Generation Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 18 X.86 Encoding and Decoding 14. Laps Encoding of MAC Frames Concept 15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Register Address Map Device RegistersBert Global Register Bit Map Register Bit MapsGlobal Register Bit Map Name Arbiter Register Bit Map Arbiter Register Bit MapBert Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h GL.IDRL Global Register DefinitionsGL.IDRH GL.CR1 GL.BLR GL.SRCALS GL.RTCAL04h Global Sdram Reference Clock Activity Latched Status GL.SIE GL.LIEGL.LIS GL.SIS GL.IBIE GL.TRQIEGL.TRQIS GL.IBIS GL.CON1 GL.C1QPR GL.IMXCN Available User Commands Value CommentGL.IMXC GL.IMXSS GL.IMXSIE GL.IMXDFEIE GL.IMXSLSGL.IMXDFD GL.IMXDFDELS GL.IMXOOFIE Inverse MUX OOF Interrupt Enable1Eh GL.BISTEN GL.IMXOOFLSGL.BISTPF GL.SDMODE2 GL.SDMODE1GL.SDMODEWS 3Dh GL.SDRFTCGlobal Sdram Refresh Time Control SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 AR.RQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.TQSC1 80h Bert RegistersBert Control Register Bit 7 This bit must be kept low for proper operation 82h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 83h Bert Pattern Byte 1 Register Bert Pattern Byte 0 Register84h 85h Bert Status Register Transmit Error Insertion Control Register88h 8Ch 8Eh Bert Status Register Interrupt EnableBert Status Register Latched 90h RBECR2 Receive Bit Count Byte 2 Register Receive Bit Count Byte 1 Register #199h 9Ah Serial Interface Transmit Register Bit Descriptions Serial Interface RegistersSerial Interface Transmit and Common Registers LI.RSTPD Transmit Packet Processor Control Low Register Transmit Hdlc Processor RegistersLI.TPPCL 0C4h LI.TIFGC LI.TEPLC LI.TEPHC Transmit Errored Packet High Control RegisterCleanup routine 0C7h LI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR2 LI.TBCR0LI.TBCR1 LI.TBCR3 LI.THPMUU LI.THPMUS LI.TRX86A 4 X.86 RegistersLI.TX86EDE LI.TRX8C LI.TRX86SAPIL LI.CIR LI.RPPCL Receive Serial InterfaceLI.RMPSCL LI.RMPSCH LI.RPPSR Receive Packet Processor Status Register Latched LI.RPPSRL105h LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC2 LI.RBC0LI.RBC1 LI.RBC3 LI.RAC2 LI.RAC0LI.RAC1 LI.RAC3 LI.RHPMUS LI.RHPMUULI.RX86S LI.RX86LSIE LI.TQLT LI.TQTIE LI.TQHTLI.TQCTLS SU.MACRADL Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADH SU.MACRD3 SU.MACRD1SU.MACRD2 SU.MACWD0 SU.MACWD3 SU.MACWD1SU.MACWD2 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR 151h SU.TFRCTransmit Frame Resend Control Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RQLT SU.RMFSRLSU.RMFSRH SU.RQHT SU.QRIE SU.QCRLS 15Eh SU.RFRCReceive Frame Rejection Control Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACAH SU.MACAL SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh MAC Reserved Control Register010Ch indirect 010Eh 0112h 0110h indirect0111h 0113h 0200h indirect SU.RxFrmCtrMAC All Frames Received Counter 0201h 0204h indirect SU.RxFrmOkCtrMAC Frames Received OK Counter 0205h 0300h indirect SU.TxFrmCtrMAC All Frames Transmitted Counter 0301h 0308h indirect SU.TxBytesCtrMAC All Bytes Transmitted Counter 0309h 030Ch indirect SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Dh SU.TXFRMUNDR 0338h indirect SU.TxBdFrmCtrMAC All Frames Aborted Counter 0339h Functional Timing MII and Rmii Interfaces MII Receive Functional Timing Operating Parameters DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Recommended DC Operating Conditions Parameter MIN TYP MAX Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow AIR Flow THETA-JA 10Mbps 100Mbps Parameter SymbolMII Interface Transmit MII Interface MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Receive Rmii Interface Timing Mdio Interface -9. Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Transmit WAN Interface 10. Transmit WAN Interface Tclki Tser Tsync Receive WAN Interface 11. Receive WAN Interface Rclki Rser Rsync 100MHz Sdram Timing 12. Sdram Interface TimingSdclko to SRAS, SCAS, SWE, Sdcs Sdata SRAS, Scas Link #1, Channel #1 Rsync Rser BIT Level Detail Rclki Rsync 10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = 15. Jtag Interface Timing Diagram Jtag Interface Timing 14. Jtag Interface Timing Jtag Functional Block Diagram Jtag Information Jtag TAP Controller State Machine Description Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Boundary Scan Register Jtag ID Codes ID Code StructureTest Registers Bypass Register Jtag Functional Timing Package Information 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Document Revision History Revision Description